stm32f1_staging/stm32f102/gpioa/
crh.rs

1///Register `CRH` reader
2pub type R = crate::R<CRHrs>;
3///Register `CRH` writer
4pub type W = crate::W<CRHrs>;
5///Field `CNF(8-15)` reader - Port n.%s configuration bits
6pub use super::crl::CNF_R;
7///Field `CNF(8-15)` writer - Port n.%s configuration bits
8pub use super::crl::CNF_W;
9///Port n.%s configuration bits
10pub use super::crl::CONFIG;
11///Port n.%s mode bits
12pub use super::crl::MODE;
13///Field `MODE(8-15)` reader - Port n.%s mode bits
14pub use super::crl::MODE_R;
15///Field `MODE(8-15)` writer - Port n.%s mode bits
16pub use super::crl::MODE_W;
17impl R {
18    ///Port n.(8-15) mode bits
19    ///
20    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE8` field.</div>
21    #[inline(always)]
22    pub fn mode(&self, n: u8) -> MODE_R {
23        #[allow(clippy::no_effect)] [(); 8][n as usize];
24        MODE_R::new(((self.bits >> (n * 4)) & 3) as u8)
25    }
26    ///Iterator for array of:
27    ///Port n.(8-15) mode bits
28    #[inline(always)]
29    pub fn mode_iter(&self) -> impl Iterator<Item = MODE_R> + '_ {
30        (0..8).map(move |n| MODE_R::new(((self.bits >> (n * 4)) & 3) as u8))
31    }
32    ///Bits 0:1 - Port n.8 mode bits
33    #[inline(always)]
34    pub fn mode8(&self) -> MODE_R {
35        MODE_R::new((self.bits & 3) as u8)
36    }
37    ///Bits 4:5 - Port n.9 mode bits
38    #[inline(always)]
39    pub fn mode9(&self) -> MODE_R {
40        MODE_R::new(((self.bits >> 4) & 3) as u8)
41    }
42    ///Bits 8:9 - Port n.10 mode bits
43    #[inline(always)]
44    pub fn mode10(&self) -> MODE_R {
45        MODE_R::new(((self.bits >> 8) & 3) as u8)
46    }
47    ///Bits 12:13 - Port n.11 mode bits
48    #[inline(always)]
49    pub fn mode11(&self) -> MODE_R {
50        MODE_R::new(((self.bits >> 12) & 3) as u8)
51    }
52    ///Bits 16:17 - Port n.12 mode bits
53    #[inline(always)]
54    pub fn mode12(&self) -> MODE_R {
55        MODE_R::new(((self.bits >> 16) & 3) as u8)
56    }
57    ///Bits 20:21 - Port n.13 mode bits
58    #[inline(always)]
59    pub fn mode13(&self) -> MODE_R {
60        MODE_R::new(((self.bits >> 20) & 3) as u8)
61    }
62    ///Bits 24:25 - Port n.14 mode bits
63    #[inline(always)]
64    pub fn mode14(&self) -> MODE_R {
65        MODE_R::new(((self.bits >> 24) & 3) as u8)
66    }
67    ///Bits 28:29 - Port n.15 mode bits
68    #[inline(always)]
69    pub fn mode15(&self) -> MODE_R {
70        MODE_R::new(((self.bits >> 28) & 3) as u8)
71    }
72    ///Port n.(8-15) configuration bits
73    ///
74    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF8` field.</div>
75    #[inline(always)]
76    pub fn cnf(&self, n: u8) -> CNF_R {
77        #[allow(clippy::no_effect)] [(); 8][n as usize];
78        CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8)
79    }
80    ///Iterator for array of:
81    ///Port n.(8-15) configuration bits
82    #[inline(always)]
83    pub fn cnf_iter(&self) -> impl Iterator<Item = CNF_R> + '_ {
84        (0..8).map(move |n| CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8))
85    }
86    ///Bits 2:3 - Port n.8 configuration bits
87    #[inline(always)]
88    pub fn cnf8(&self) -> CNF_R {
89        CNF_R::new(((self.bits >> 2) & 3) as u8)
90    }
91    ///Bits 6:7 - Port n.9 configuration bits
92    #[inline(always)]
93    pub fn cnf9(&self) -> CNF_R {
94        CNF_R::new(((self.bits >> 6) & 3) as u8)
95    }
96    ///Bits 10:11 - Port n.10 configuration bits
97    #[inline(always)]
98    pub fn cnf10(&self) -> CNF_R {
99        CNF_R::new(((self.bits >> 10) & 3) as u8)
100    }
101    ///Bits 14:15 - Port n.11 configuration bits
102    #[inline(always)]
103    pub fn cnf11(&self) -> CNF_R {
104        CNF_R::new(((self.bits >> 14) & 3) as u8)
105    }
106    ///Bits 18:19 - Port n.12 configuration bits
107    #[inline(always)]
108    pub fn cnf12(&self) -> CNF_R {
109        CNF_R::new(((self.bits >> 18) & 3) as u8)
110    }
111    ///Bits 22:23 - Port n.13 configuration bits
112    #[inline(always)]
113    pub fn cnf13(&self) -> CNF_R {
114        CNF_R::new(((self.bits >> 22) & 3) as u8)
115    }
116    ///Bits 26:27 - Port n.14 configuration bits
117    #[inline(always)]
118    pub fn cnf14(&self) -> CNF_R {
119        CNF_R::new(((self.bits >> 26) & 3) as u8)
120    }
121    ///Bits 30:31 - Port n.15 configuration bits
122    #[inline(always)]
123    pub fn cnf15(&self) -> CNF_R {
124        CNF_R::new(((self.bits >> 30) & 3) as u8)
125    }
126}
127impl core::fmt::Debug for R {
128    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
129        f.debug_struct("CRH")
130            .field("mode8", &self.mode8())
131            .field("mode9", &self.mode9())
132            .field("mode10", &self.mode10())
133            .field("mode11", &self.mode11())
134            .field("mode12", &self.mode12())
135            .field("mode13", &self.mode13())
136            .field("mode14", &self.mode14())
137            .field("mode15", &self.mode15())
138            .field("cnf8", &self.cnf8())
139            .field("cnf9", &self.cnf9())
140            .field("cnf10", &self.cnf10())
141            .field("cnf11", &self.cnf11())
142            .field("cnf12", &self.cnf12())
143            .field("cnf13", &self.cnf13())
144            .field("cnf14", &self.cnf14())
145            .field("cnf15", &self.cnf15())
146            .finish()
147    }
148}
149impl W {
150    ///Port n.(8-15) mode bits
151    ///
152    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE8` field.</div>
153    #[inline(always)]
154    pub fn mode(&mut self, n: u8) -> MODE_W<CRHrs> {
155        #[allow(clippy::no_effect)] [(); 8][n as usize];
156        MODE_W::new(self, n * 4)
157    }
158    ///Bits 0:1 - Port n.8 mode bits
159    #[inline(always)]
160    pub fn mode8(&mut self) -> MODE_W<CRHrs> {
161        MODE_W::new(self, 0)
162    }
163    ///Bits 4:5 - Port n.9 mode bits
164    #[inline(always)]
165    pub fn mode9(&mut self) -> MODE_W<CRHrs> {
166        MODE_W::new(self, 4)
167    }
168    ///Bits 8:9 - Port n.10 mode bits
169    #[inline(always)]
170    pub fn mode10(&mut self) -> MODE_W<CRHrs> {
171        MODE_W::new(self, 8)
172    }
173    ///Bits 12:13 - Port n.11 mode bits
174    #[inline(always)]
175    pub fn mode11(&mut self) -> MODE_W<CRHrs> {
176        MODE_W::new(self, 12)
177    }
178    ///Bits 16:17 - Port n.12 mode bits
179    #[inline(always)]
180    pub fn mode12(&mut self) -> MODE_W<CRHrs> {
181        MODE_W::new(self, 16)
182    }
183    ///Bits 20:21 - Port n.13 mode bits
184    #[inline(always)]
185    pub fn mode13(&mut self) -> MODE_W<CRHrs> {
186        MODE_W::new(self, 20)
187    }
188    ///Bits 24:25 - Port n.14 mode bits
189    #[inline(always)]
190    pub fn mode14(&mut self) -> MODE_W<CRHrs> {
191        MODE_W::new(self, 24)
192    }
193    ///Bits 28:29 - Port n.15 mode bits
194    #[inline(always)]
195    pub fn mode15(&mut self) -> MODE_W<CRHrs> {
196        MODE_W::new(self, 28)
197    }
198    ///Port n.(8-15) configuration bits
199    ///
200    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF8` field.</div>
201    #[inline(always)]
202    pub fn cnf(&mut self, n: u8) -> CNF_W<CRHrs> {
203        #[allow(clippy::no_effect)] [(); 8][n as usize];
204        CNF_W::new(self, n * 4 + 2)
205    }
206    ///Bits 2:3 - Port n.8 configuration bits
207    #[inline(always)]
208    pub fn cnf8(&mut self) -> CNF_W<CRHrs> {
209        CNF_W::new(self, 2)
210    }
211    ///Bits 6:7 - Port n.9 configuration bits
212    #[inline(always)]
213    pub fn cnf9(&mut self) -> CNF_W<CRHrs> {
214        CNF_W::new(self, 6)
215    }
216    ///Bits 10:11 - Port n.10 configuration bits
217    #[inline(always)]
218    pub fn cnf10(&mut self) -> CNF_W<CRHrs> {
219        CNF_W::new(self, 10)
220    }
221    ///Bits 14:15 - Port n.11 configuration bits
222    #[inline(always)]
223    pub fn cnf11(&mut self) -> CNF_W<CRHrs> {
224        CNF_W::new(self, 14)
225    }
226    ///Bits 18:19 - Port n.12 configuration bits
227    #[inline(always)]
228    pub fn cnf12(&mut self) -> CNF_W<CRHrs> {
229        CNF_W::new(self, 18)
230    }
231    ///Bits 22:23 - Port n.13 configuration bits
232    #[inline(always)]
233    pub fn cnf13(&mut self) -> CNF_W<CRHrs> {
234        CNF_W::new(self, 22)
235    }
236    ///Bits 26:27 - Port n.14 configuration bits
237    #[inline(always)]
238    pub fn cnf14(&mut self) -> CNF_W<CRHrs> {
239        CNF_W::new(self, 26)
240    }
241    ///Bits 30:31 - Port n.15 configuration bits
242    #[inline(always)]
243    pub fn cnf15(&mut self) -> CNF_W<CRHrs> {
244        CNF_W::new(self, 30)
245    }
246}
247/**Port configuration register high (GPIOn_CRL)
248
249You can [`read`](crate::Reg::read) this register and get [`crh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:CRH)*/
252pub struct CRHrs;
253impl crate::RegisterSpec for CRHrs {
254    type Ux = u32;
255}
256///`read()` method returns [`crh::R`](R) reader structure
257impl crate::Readable for CRHrs {}
258///`write(|w| ..)` method takes [`crh::W`](W) writer structure
259impl crate::Writable for CRHrs {
260    type Safety = crate::Unsafe;
261}
262///`reset()` method sets CRH to value 0x4444_4444
263impl crate::Resettable for CRHrs {
264    const RESET_VALUE: u32 = 0x4444_4444;
265}
stm32f1_staging/stm32f102/gpioa/crh.rs

stm32f1_staging/stm32f102/gpioa/
crh.rs
