stm32f1_staging/stm32f102/flash/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5///Field `BSY` reader - Busy
6pub type BSY_R = crate::BitReader;
7///Field `PGERR` reader - Programming error
8pub type PGERR_R = crate::BitReader;
9///Field `PGERR` writer - Programming error
10pub type PGERR_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `WRPRTERR` reader - Write protection error
12pub type WRPRTERR_R = crate::BitReader;
13///Field `WRPRTERR` writer - Write protection error
14pub type WRPRTERR_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `EOP` reader - End of operation
16pub type EOP_R = crate::BitReader;
17///Field `EOP` writer - End of operation
18pub type EOP_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    ///Bit 0 - Busy
21    #[inline(always)]
22    pub fn bsy(&self) -> BSY_R {
23        BSY_R::new((self.bits & 1) != 0)
24    }
25    ///Bit 2 - Programming error
26    #[inline(always)]
27    pub fn pgerr(&self) -> PGERR_R {
28        PGERR_R::new(((self.bits >> 2) & 1) != 0)
29    }
30    ///Bit 4 - Write protection error
31    #[inline(always)]
32    pub fn wrprterr(&self) -> WRPRTERR_R {
33        WRPRTERR_R::new(((self.bits >> 4) & 1) != 0)
34    }
35    ///Bit 5 - End of operation
36    #[inline(always)]
37    pub fn eop(&self) -> EOP_R {
38        EOP_R::new(((self.bits >> 5) & 1) != 0)
39    }
40}
41impl core::fmt::Debug for R {
42    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
43        f.debug_struct("SR")
44            .field("eop", &self.eop())
45            .field("wrprterr", &self.wrprterr())
46            .field("pgerr", &self.pgerr())
47            .field("bsy", &self.bsy())
48            .finish()
49    }
50}
51impl W {
52    ///Bit 2 - Programming error
53    #[inline(always)]
54    pub fn pgerr(&mut self) -> PGERR_W<SRrs> {
55        PGERR_W::new(self, 2)
56    }
57    ///Bit 4 - Write protection error
58    #[inline(always)]
59    pub fn wrprterr(&mut self) -> WRPRTERR_W<SRrs> {
60        WRPRTERR_W::new(self, 4)
61    }
62    ///Bit 5 - End of operation
63    #[inline(always)]
64    pub fn eop(&mut self) -> EOP_W<SRrs> {
65        EOP_W::new(self, 5)
66    }
67}
68/**Status register
69
70You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
71
72See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#FLASH:SR)*/
73pub struct SRrs;
74impl crate::RegisterSpec for SRrs {
75    type Ux = u32;
76}
77///`read()` method returns [`sr::R`](R) reader structure
78impl crate::Readable for SRrs {}
79///`write(|w| ..)` method takes [`sr::W`](W) writer structure
80impl crate::Writable for SRrs {
81    type Safety = crate::Unsafe;
82}
83///`reset()` method sets SR to value 0
84impl crate::Resettable for SRrs {}
stm32f1_staging/stm32f102/flash/sr.rs

stm32f1_staging/stm32f102/flash/
sr.rs
