stm32f1_staging/stm32f102/dbgmcu/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `DBG_SLEEP` reader - DBG_SLEEP
6pub type DBG_SLEEP_R = crate::BitReader;
7///Field `DBG_SLEEP` writer - DBG_SLEEP
8pub type DBG_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DBG_STOP` reader - DBG_STOP
10pub type DBG_STOP_R = crate::BitReader;
11///Field `DBG_STOP` writer - DBG_STOP
12pub type DBG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DBG_STANDBY` reader - DBG_STANDBY
14pub type DBG_STANDBY_R = crate::BitReader;
15///Field `DBG_STANDBY` writer - DBG_STANDBY
16pub type DBG_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `TRACE_IOEN` reader - TRACE_IOEN
18pub type TRACE_IOEN_R = crate::BitReader;
19///Field `TRACE_IOEN` writer - TRACE_IOEN
20pub type TRACE_IOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TRACE_MODE` reader - TRACE_MODE
22pub type TRACE_MODE_R = crate::FieldReader;
23///Field `TRACE_MODE` writer - TRACE_MODE
24pub type TRACE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `DBG_IWDG_STOP` reader - DBG_IWDG_STOP
26pub type DBG_IWDG_STOP_R = crate::BitReader;
27///Field `DBG_IWDG_STOP` writer - DBG_IWDG_STOP
28pub type DBG_IWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP
30pub type DBG_WWDG_STOP_R = crate::BitReader;
31///Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP
32pub type DBG_WWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP
34pub type DBG_TIM2_STOP_R = crate::BitReader;
35///Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP
36pub type DBG_TIM2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DBG_TIM3_STOP` reader - DBG_TIM3_STOP
38pub type DBG_TIM3_STOP_R = crate::BitReader;
39///Field `DBG_TIM3_STOP` writer - DBG_TIM3_STOP
40pub type DBG_TIM3_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DBG_I2C1_SMBUS_TIMEOUT` reader - DBG_I2C1_SMBUS_TIMEOUT
42pub type DBG_I2C1_SMBUS_TIMEOUT_R = crate::BitReader;
43///Field `DBG_I2C1_SMBUS_TIMEOUT` writer - DBG_I2C1_SMBUS_TIMEOUT
44pub type DBG_I2C1_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    ///Bit 0 - DBG_SLEEP
47    #[inline(always)]
48    pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
49        DBG_SLEEP_R::new((self.bits & 1) != 0)
50    }
51    ///Bit 1 - DBG_STOP
52    #[inline(always)]
53    pub fn dbg_stop(&self) -> DBG_STOP_R {
54        DBG_STOP_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    ///Bit 2 - DBG_STANDBY
57    #[inline(always)]
58    pub fn dbg_standby(&self) -> DBG_STANDBY_R {
59        DBG_STANDBY_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    ///Bit 5 - TRACE_IOEN
62    #[inline(always)]
63    pub fn trace_ioen(&self) -> TRACE_IOEN_R {
64        TRACE_IOEN_R::new(((self.bits >> 5) & 1) != 0)
65    }
66    ///Bits 6:7 - TRACE_MODE
67    #[inline(always)]
68    pub fn trace_mode(&self) -> TRACE_MODE_R {
69        TRACE_MODE_R::new(((self.bits >> 6) & 3) as u8)
70    }
71    ///Bit 8 - DBG_IWDG_STOP
72    #[inline(always)]
73    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
74        DBG_IWDG_STOP_R::new(((self.bits >> 8) & 1) != 0)
75    }
76    ///Bit 9 - DBG_WWDG_STOP
77    #[inline(always)]
78    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
79        DBG_WWDG_STOP_R::new(((self.bits >> 9) & 1) != 0)
80    }
81    ///Bit 11 - DBG_TIM2_STOP
82    #[inline(always)]
83    pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R {
84        DBG_TIM2_STOP_R::new(((self.bits >> 11) & 1) != 0)
85    }
86    ///Bit 12 - DBG_TIM3_STOP
87    #[inline(always)]
88    pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R {
89        DBG_TIM3_STOP_R::new(((self.bits >> 12) & 1) != 0)
90    }
91    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
92    #[inline(always)]
93    pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R {
94        DBG_I2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 15) & 1) != 0)
95    }
96}
97impl core::fmt::Debug for R {
98    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99        f.debug_struct("CR")
100            .field("dbg_sleep", &self.dbg_sleep())
101            .field("dbg_stop", &self.dbg_stop())
102            .field("dbg_standby", &self.dbg_standby())
103            .field("trace_ioen", &self.trace_ioen())
104            .field("trace_mode", &self.trace_mode())
105            .field("dbg_iwdg_stop", &self.dbg_iwdg_stop())
106            .field("dbg_wwdg_stop", &self.dbg_wwdg_stop())
107            .field("dbg_tim2_stop", &self.dbg_tim2_stop())
108            .field("dbg_tim3_stop", &self.dbg_tim3_stop())
109            .field("dbg_i2c1_smbus_timeout", &self.dbg_i2c1_smbus_timeout())
110            .finish()
111    }
112}
113impl W {
114    ///Bit 0 - DBG_SLEEP
115    #[inline(always)]
116    pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<CRrs> {
117        DBG_SLEEP_W::new(self, 0)
118    }
119    ///Bit 1 - DBG_STOP
120    #[inline(always)]
121    pub fn dbg_stop(&mut self) -> DBG_STOP_W<CRrs> {
122        DBG_STOP_W::new(self, 1)
123    }
124    ///Bit 2 - DBG_STANDBY
125    #[inline(always)]
126    pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<CRrs> {
127        DBG_STANDBY_W::new(self, 2)
128    }
129    ///Bit 5 - TRACE_IOEN
130    #[inline(always)]
131    pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<CRrs> {
132        TRACE_IOEN_W::new(self, 5)
133    }
134    ///Bits 6:7 - TRACE_MODE
135    #[inline(always)]
136    pub fn trace_mode(&mut self) -> TRACE_MODE_W<CRrs> {
137        TRACE_MODE_W::new(self, 6)
138    }
139    ///Bit 8 - DBG_IWDG_STOP
140    #[inline(always)]
141    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<CRrs> {
142        DBG_IWDG_STOP_W::new(self, 8)
143    }
144    ///Bit 9 - DBG_WWDG_STOP
145    #[inline(always)]
146    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<CRrs> {
147        DBG_WWDG_STOP_W::new(self, 9)
148    }
149    ///Bit 11 - DBG_TIM2_STOP
150    #[inline(always)]
151    pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<CRrs> {
152        DBG_TIM2_STOP_W::new(self, 11)
153    }
154    ///Bit 12 - DBG_TIM3_STOP
155    #[inline(always)]
156    pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<CRrs> {
157        DBG_TIM3_STOP_W::new(self, 12)
158    }
159    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
160    #[inline(always)]
161    pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<CRrs> {
162        DBG_I2C1_SMBUS_TIMEOUT_W::new(self, 15)
163    }
164}
165/**DBGMCU_CR
166
167You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DBGMCU:CR)*/
170pub struct CRrs;
171impl crate::RegisterSpec for CRrs {
172    type Ux = u32;
173}
174///`read()` method returns [`cr::R`](R) reader structure
175impl crate::Readable for CRrs {}
176///`write(|w| ..)` method takes [`cr::W`](W) writer structure
177impl crate::Writable for CRrs {
178    type Safety = crate::Unsafe;
179}
180///`reset()` method sets CR to value 0
181impl crate::Resettable for CRrs {}
stm32f1_staging/stm32f102/dbgmcu/cr.rs

stm32f1_staging/stm32f102/dbgmcu/
cr.rs
