stm32f1_staging/stm32f102/bkp/
rtccr.rs

1///Register `RTCCR` reader
2pub type R = crate::R<RTCCRrs>;
3///Register `RTCCR` writer
4pub type W = crate::W<RTCCRrs>;
5///Field `CAL` reader - Calibration value
6pub type CAL_R = crate::FieldReader;
7///Field `CAL` writer - Calibration value
8pub type CAL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9///Field `CCO` reader - Calibration Clock Output
10pub type CCO_R = crate::BitReader;
11///Field `CCO` writer - Calibration Clock Output
12pub type CCO_W<'a, REG> = crate::BitWriter<'a, REG>;
13/**Alarm or second output enable
14
15Value on reset: 0*/
16#[cfg_attr(feature = "defmt", derive(defmt::Format))]
17#[derive(Clone, Copy, Debug, PartialEq, Eq)]
18pub enum ASOE {
19    ///0: Disabled
20    Disabled = 0,
21    ///1: Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit
22    Enabled = 1,
23}
24impl From<ASOE> for bool {
25    #[inline(always)]
26    fn from(variant: ASOE) -> Self {
27        variant as u8 != 0
28    }
29}
30///Field `ASOE` reader - Alarm or second output enable
31pub type ASOE_R = crate::BitReader<ASOE>;
32impl ASOE_R {
33    ///Get enumerated values variant
34    #[inline(always)]
35    pub const fn variant(&self) -> ASOE {
36        match self.bits {
37            false => ASOE::Disabled,
38            true => ASOE::Enabled,
39        }
40    }
41    ///Disabled
42    #[inline(always)]
43    pub fn is_disabled(&self) -> bool {
44        *self == ASOE::Disabled
45    }
46    ///Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit
47    #[inline(always)]
48    pub fn is_enabled(&self) -> bool {
49        *self == ASOE::Enabled
50    }
51}
52///Field `ASOE` writer - Alarm or second output enable
53pub type ASOE_W<'a, REG> = crate::BitWriter<'a, REG, ASOE>;
54impl<'a, REG> ASOE_W<'a, REG>
55where
56    REG: crate::Writable + crate::RegisterSpec,
57{
58    ///Disabled
59    #[inline(always)]
60    pub fn disabled(self) -> &'a mut crate::W<REG> {
61        self.variant(ASOE::Disabled)
62    }
63    ///Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit
64    #[inline(always)]
65    pub fn enabled(self) -> &'a mut crate::W<REG> {
66        self.variant(ASOE::Enabled)
67    }
68}
69/**Alarm or second output selection
70
71Value on reset: 0*/
72#[cfg_attr(feature = "defmt", derive(defmt::Format))]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum ASOS {
75    ///0: RTC Alarm pulse output selected
76    Alarm = 0,
77    ///1: RTC Second pulse output selected
78    Second = 1,
79}
80impl From<ASOS> for bool {
81    #[inline(always)]
82    fn from(variant: ASOS) -> Self {
83        variant as u8 != 0
84    }
85}
86///Field `ASOS` reader - Alarm or second output selection
87pub type ASOS_R = crate::BitReader<ASOS>;
88impl ASOS_R {
89    ///Get enumerated values variant
90    #[inline(always)]
91    pub const fn variant(&self) -> ASOS {
92        match self.bits {
93            false => ASOS::Alarm,
94            true => ASOS::Second,
95        }
96    }
97    ///RTC Alarm pulse output selected
98    #[inline(always)]
99    pub fn is_alarm(&self) -> bool {
100        *self == ASOS::Alarm
101    }
102    ///RTC Second pulse output selected
103    #[inline(always)]
104    pub fn is_second(&self) -> bool {
105        *self == ASOS::Second
106    }
107}
108///Field `ASOS` writer - Alarm or second output selection
109pub type ASOS_W<'a, REG> = crate::BitWriter<'a, REG, ASOS>;
110impl<'a, REG> ASOS_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113{
114    ///RTC Alarm pulse output selected
115    #[inline(always)]
116    pub fn alarm(self) -> &'a mut crate::W<REG> {
117        self.variant(ASOS::Alarm)
118    }
119    ///RTC Second pulse output selected
120    #[inline(always)]
121    pub fn second(self) -> &'a mut crate::W<REG> {
122        self.variant(ASOS::Second)
123    }
124}
125impl R {
126    ///Bits 0:6 - Calibration value
127    #[inline(always)]
128    pub fn cal(&self) -> CAL_R {
129        CAL_R::new((self.bits & 0x7f) as u8)
130    }
131    ///Bit 7 - Calibration Clock Output
132    #[inline(always)]
133    pub fn cco(&self) -> CCO_R {
134        CCO_R::new(((self.bits >> 7) & 1) != 0)
135    }
136    ///Bit 8 - Alarm or second output enable
137    #[inline(always)]
138    pub fn asoe(&self) -> ASOE_R {
139        ASOE_R::new(((self.bits >> 8) & 1) != 0)
140    }
141    ///Bit 9 - Alarm or second output selection
142    #[inline(always)]
143    pub fn asos(&self) -> ASOS_R {
144        ASOS_R::new(((self.bits >> 9) & 1) != 0)
145    }
146}
147impl core::fmt::Debug for R {
148    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
149        f.debug_struct("RTCCR")
150            .field("cal", &self.cal())
151            .field("cco", &self.cco())
152            .field("asoe", &self.asoe())
153            .field("asos", &self.asos())
154            .finish()
155    }
156}
157impl W {
158    ///Bits 0:6 - Calibration value
159    #[inline(always)]
160    pub fn cal(&mut self) -> CAL_W<RTCCRrs> {
161        CAL_W::new(self, 0)
162    }
163    ///Bit 7 - Calibration Clock Output
164    #[inline(always)]
165    pub fn cco(&mut self) -> CCO_W<RTCCRrs> {
166        CCO_W::new(self, 7)
167    }
168    ///Bit 8 - Alarm or second output enable
169    #[inline(always)]
170    pub fn asoe(&mut self) -> ASOE_W<RTCCRrs> {
171        ASOE_W::new(self, 8)
172    }
173    ///Bit 9 - Alarm or second output selection
174    #[inline(always)]
175    pub fn asos(&mut self) -> ASOS_W<RTCCRrs> {
176        ASOS_W::new(self, 9)
177    }
178}
179/**RTC clock calibration register (BKP_RTCCR)
180
181You can [`read`](crate::Reg::read) this register and get [`rtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
182
183See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#BKP:RTCCR)*/
184pub struct RTCCRrs;
185impl crate::RegisterSpec for RTCCRrs {
186    type Ux = u32;
187}
188///`read()` method returns [`rtccr::R`](R) reader structure
189impl crate::Readable for RTCCRrs {}
190///`write(|w| ..)` method takes [`rtccr::W`](W) writer structure
191impl crate::Writable for RTCCRrs {
192    type Safety = crate::Unsafe;
193}
194///`reset()` method sets RTCCR to value 0
195impl crate::Resettable for RTCCRrs {}
stm32f1_staging/stm32f102/bkp/rtccr.rs

stm32f1_staging/stm32f102/bkp/
rtccr.rs
