stm32f1_staging/stm32f102/afio/
exticr4.rs

1///Register `EXTICR4` reader
2pub type R = crate::R<EXTICR4rs>;
3///Register `EXTICR4` writer
4pub type W = crate::W<EXTICR4rs>;
5///EXTI12 configuration
6pub use super::exticr1::EXTI0;
7///Field `EXTI12` reader - EXTI12 configuration
8pub use super::exticr1::EXTI0_R as EXTI12_R;
9///Field `EXTI13` reader - EXTI13 configuration
10pub use super::exticr1::EXTI0_R as EXTI13_R;
11///Field `EXTI14` reader - EXTI14 configuration
12pub use super::exticr1::EXTI0_R as EXTI14_R;
13///Field `EXTI15` reader - EXTI15 configuration
14pub use super::exticr1::EXTI0_R as EXTI15_R;
15///Field `EXTI12` writer - EXTI12 configuration
16pub use super::exticr1::EXTI0_W as EXTI12_W;
17///Field `EXTI13` writer - EXTI13 configuration
18pub use super::exticr1::EXTI0_W as EXTI13_W;
19///Field `EXTI14` writer - EXTI14 configuration
20pub use super::exticr1::EXTI0_W as EXTI14_W;
21///Field `EXTI15` writer - EXTI15 configuration
22pub use super::exticr1::EXTI0_W as EXTI15_W;
23impl R {
24    ///Bits 0:3 - EXTI12 configuration
25    #[inline(always)]
26    pub fn exti12(&self) -> EXTI12_R {
27        EXTI12_R::new((self.bits & 0x0f) as u8)
28    }
29    ///Bits 4:7 - EXTI13 configuration
30    #[inline(always)]
31    pub fn exti13(&self) -> EXTI13_R {
32        EXTI13_R::new(((self.bits >> 4) & 0x0f) as u8)
33    }
34    ///Bits 8:11 - EXTI14 configuration
35    #[inline(always)]
36    pub fn exti14(&self) -> EXTI14_R {
37        EXTI14_R::new(((self.bits >> 8) & 0x0f) as u8)
38    }
39    ///Bits 12:15 - EXTI15 configuration
40    #[inline(always)]
41    pub fn exti15(&self) -> EXTI15_R {
42        EXTI15_R::new(((self.bits >> 12) & 0x0f) as u8)
43    }
44}
45impl core::fmt::Debug for R {
46    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
47        f.debug_struct("EXTICR4")
48            .field("exti12", &self.exti12())
49            .field("exti13", &self.exti13())
50            .field("exti14", &self.exti14())
51            .field("exti15", &self.exti15())
52            .finish()
53    }
54}
55impl W {
56    ///Bits 0:3 - EXTI12 configuration
57    #[inline(always)]
58    pub fn exti12(&mut self) -> EXTI12_W<EXTICR4rs> {
59        EXTI12_W::new(self, 0)
60    }
61    ///Bits 4:7 - EXTI13 configuration
62    #[inline(always)]
63    pub fn exti13(&mut self) -> EXTI13_W<EXTICR4rs> {
64        EXTI13_W::new(self, 4)
65    }
66    ///Bits 8:11 - EXTI14 configuration
67    #[inline(always)]
68    pub fn exti14(&mut self) -> EXTI14_W<EXTICR4rs> {
69        EXTI14_W::new(self, 8)
70    }
71    ///Bits 12:15 - EXTI15 configuration
72    #[inline(always)]
73    pub fn exti15(&mut self) -> EXTI15_W<EXTICR4rs> {
74        EXTI15_W::new(self, 12)
75    }
76}
77/**External interrupt configuration register 4 (AFIO_EXTICR4)
78
79You can [`read`](crate::Reg::read) this register and get [`exticr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#AFIO:EXTICR4)*/
82pub struct EXTICR4rs;
83impl crate::RegisterSpec for EXTICR4rs {
84    type Ux = u32;
85}
86///`read()` method returns [`exticr4::R`](R) reader structure
87impl crate::Readable for EXTICR4rs {}
88///`write(|w| ..)` method takes [`exticr4::W`](W) writer structure
89impl crate::Writable for EXTICR4rs {
90    type Safety = crate::Unsafe;
91}
92///`reset()` method sets EXTICR4 to value 0
93impl crate::Resettable for EXTICR4rs {}
stm32f1_staging/stm32f102/afio/exticr4.rs

stm32f1_staging/stm32f102/afio/
exticr4.rs
