stm32f1_staging/stm32f102/adc1/
sqr3.rs

1///Register `SQR3` reader
2pub type R = crate::R<SQR3rs>;
3///Register `SQR3` writer
4pub type W = crate::W<SQR3rs>;
5///Field `SQ(1-6)` reader - %s conversion in regular sequence
6pub type SQ_R = crate::FieldReader;
7///Field `SQ(1-6)` writer - %s conversion in regular sequence
8pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9impl R {
10    ///(1-6) conversion in regular sequence
11    ///
12    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
13    #[inline(always)]
14    pub fn sq(&self, n: u8) -> SQ_R {
15        #[allow(clippy::no_effect)] [(); 6][n as usize];
16        SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8)
17    }
18    ///Iterator for array of:
19    ///(1-6) conversion in regular sequence
20    #[inline(always)]
21    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
22        (0..6).map(move |n| SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8))
23    }
24    ///Bits 0:4 - 1 conversion in regular sequence
25    #[inline(always)]
26    pub fn sq1(&self) -> SQ_R {
27        SQ_R::new((self.bits & 0x1f) as u8)
28    }
29    ///Bits 5:9 - 2 conversion in regular sequence
30    #[inline(always)]
31    pub fn sq2(&self) -> SQ_R {
32        SQ_R::new(((self.bits >> 5) & 0x1f) as u8)
33    }
34    ///Bits 10:14 - 3 conversion in regular sequence
35    #[inline(always)]
36    pub fn sq3(&self) -> SQ_R {
37        SQ_R::new(((self.bits >> 10) & 0x1f) as u8)
38    }
39    ///Bits 15:19 - 4 conversion in regular sequence
40    #[inline(always)]
41    pub fn sq4(&self) -> SQ_R {
42        SQ_R::new(((self.bits >> 15) & 0x1f) as u8)
43    }
44    ///Bits 20:24 - 5 conversion in regular sequence
45    #[inline(always)]
46    pub fn sq5(&self) -> SQ_R {
47        SQ_R::new(((self.bits >> 20) & 0x1f) as u8)
48    }
49    ///Bits 25:29 - 6 conversion in regular sequence
50    #[inline(always)]
51    pub fn sq6(&self) -> SQ_R {
52        SQ_R::new(((self.bits >> 25) & 0x1f) as u8)
53    }
54}
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("SQR3")
58            .field("sq1", &self.sq1())
59            .field("sq2", &self.sq2())
60            .field("sq3", &self.sq3())
61            .field("sq4", &self.sq4())
62            .field("sq5", &self.sq5())
63            .field("sq6", &self.sq6())
64            .finish()
65    }
66}
67impl W {
68    ///(1-6) conversion in regular sequence
69    ///
70    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
71    #[inline(always)]
72    pub fn sq(&mut self, n: u8) -> SQ_W<SQR3rs> {
73        #[allow(clippy::no_effect)] [(); 6][n as usize];
74        SQ_W::new(self, n * 5)
75    }
76    ///Bits 0:4 - 1 conversion in regular sequence
77    #[inline(always)]
78    pub fn sq1(&mut self) -> SQ_W<SQR3rs> {
79        SQ_W::new(self, 0)
80    }
81    ///Bits 5:9 - 2 conversion in regular sequence
82    #[inline(always)]
83    pub fn sq2(&mut self) -> SQ_W<SQR3rs> {
84        SQ_W::new(self, 5)
85    }
86    ///Bits 10:14 - 3 conversion in regular sequence
87    #[inline(always)]
88    pub fn sq3(&mut self) -> SQ_W<SQR3rs> {
89        SQ_W::new(self, 10)
90    }
91    ///Bits 15:19 - 4 conversion in regular sequence
92    #[inline(always)]
93    pub fn sq4(&mut self) -> SQ_W<SQR3rs> {
94        SQ_W::new(self, 15)
95    }
96    ///Bits 20:24 - 5 conversion in regular sequence
97    #[inline(always)]
98    pub fn sq5(&mut self) -> SQ_W<SQR3rs> {
99        SQ_W::new(self, 20)
100    }
101    ///Bits 25:29 - 6 conversion in regular sequence
102    #[inline(always)]
103    pub fn sq6(&mut self) -> SQ_W<SQR3rs> {
104        SQ_W::new(self, 25)
105    }
106}
107/**regular sequence register 3
108
109You can [`read`](crate::Reg::read) this register and get [`sqr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
110
111See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC1:SQR3)*/
112pub struct SQR3rs;
113impl crate::RegisterSpec for SQR3rs {
114    type Ux = u32;
115}
116///`read()` method returns [`sqr3::R`](R) reader structure
117impl crate::Readable for SQR3rs {}
118///`write(|w| ..)` method takes [`sqr3::W`](W) writer structure
119impl crate::Writable for SQR3rs {
120    type Safety = crate::Unsafe;
121}
122///`reset()` method sets SQR3 to value 0
123impl crate::Resettable for SQR3rs {}
stm32f1_staging/stm32f102/adc1/sqr3.rs

stm32f1_staging/stm32f102/adc1/
sqr3.rs
