stm32f1_staging/stm32f101/tim9/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Update interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIFR {
11    ///0: No update occurred
12    NoUpdateOccurred = 0,
13    ///1: Update interrupt pending
14    UpdatePending = 1,
15}
16impl From<UIFR> for bool {
17    #[inline(always)]
18    fn from(variant: UIFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIF` reader - Update interrupt flag
23pub type UIF_R = crate::BitReader<UIFR>;
24impl UIF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIFR {
28        match self.bits {
29            false => UIFR::NoUpdateOccurred,
30            true => UIFR::UpdatePending,
31        }
32    }
33    ///No update occurred
34    #[inline(always)]
35    pub fn is_no_update_occurred(&self) -> bool {
36        *self == UIFR::NoUpdateOccurred
37    }
38    ///Update interrupt pending
39    #[inline(always)]
40    pub fn is_update_pending(&self) -> bool {
41        *self == UIFR::UpdatePending
42    }
43}
44/**Update interrupt flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum UIFW {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<UIFW> for bool {
54    #[inline(always)]
55    fn from(variant: UIFW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `UIF` writer - Update interrupt flag
60pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
61impl<'a, REG> UIF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(UIFW::Clear)
69    }
70}
71/**Capture/compare %s interrupt flag
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum CC1IFR {
77    ///0: No campture/compare has been detected
78    NoMatch = 0,
79    ///1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
80    Match = 1,
81}
82impl From<CC1IFR> for bool {
83    #[inline(always)]
84    fn from(variant: CC1IFR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `CCIF(1-2)` reader - Capture/compare %s interrupt flag
89pub type CCIF_R = crate::BitReader<CC1IFR>;
90impl CCIF_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> CC1IFR {
94        match self.bits {
95            false => CC1IFR::NoMatch,
96            true => CC1IFR::Match,
97        }
98    }
99    ///No campture/compare has been detected
100    #[inline(always)]
101    pub fn is_no_match(&self) -> bool {
102        *self == CC1IFR::NoMatch
103    }
104    ///If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
105    #[inline(always)]
106    pub fn is_match(&self) -> bool {
107        *self == CC1IFR::Match
108    }
109}
110/**Capture/compare %s interrupt flag
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CC1IFW {
116    ///0: Clear flag
117    Clear = 0,
118}
119impl From<CC1IFW> for bool {
120    #[inline(always)]
121    fn from(variant: CC1IFW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `CCIF(1-2)` writer - Capture/compare %s interrupt flag
126pub type CCIF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1IFW>;
127impl<'a, REG> CCIF_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(CC1IFW::Clear)
135    }
136}
137/**Trigger interrupt flag
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum TIFR {
143    ///0: No trigger event occurred
144    NoTrigger = 0,
145    ///1: Trigger interrupt pending
146    Trigger = 1,
147}
148impl From<TIFR> for bool {
149    #[inline(always)]
150    fn from(variant: TIFR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `TIF` reader - Trigger interrupt flag
155pub type TIF_R = crate::BitReader<TIFR>;
156impl TIF_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> TIFR {
160        match self.bits {
161            false => TIFR::NoTrigger,
162            true => TIFR::Trigger,
163        }
164    }
165    ///No trigger event occurred
166    #[inline(always)]
167    pub fn is_no_trigger(&self) -> bool {
168        *self == TIFR::NoTrigger
169    }
170    ///Trigger interrupt pending
171    #[inline(always)]
172    pub fn is_trigger(&self) -> bool {
173        *self == TIFR::Trigger
174    }
175}
176/**Trigger interrupt flag
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum TIFW {
182    ///0: Clear flag
183    Clear = 0,
184}
185impl From<TIFW> for bool {
186    #[inline(always)]
187    fn from(variant: TIFW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `TIF` writer - Trigger interrupt flag
192pub type TIF_W<'a, REG> = crate::BitWriter0C<'a, REG, TIFW>;
193impl<'a, REG> TIF_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(TIFW::Clear)
201    }
202}
203/**Capture/Compare %s overcapture flag
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum CC1OFR {
209    ///0: No overcapture has been detected
210    NoOvercapture = 0,
211    ///1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
212    Overcapture = 1,
213}
214impl From<CC1OFR> for bool {
215    #[inline(always)]
216    fn from(variant: CC1OFR) -> Self {
217        variant as u8 != 0
218    }
219}
220///Field `CCOF(1-2)` reader - Capture/Compare %s overcapture flag
221pub type CCOF_R = crate::BitReader<CC1OFR>;
222impl CCOF_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> CC1OFR {
226        match self.bits {
227            false => CC1OFR::NoOvercapture,
228            true => CC1OFR::Overcapture,
229        }
230    }
231    ///No overcapture has been detected
232    #[inline(always)]
233    pub fn is_no_overcapture(&self) -> bool {
234        *self == CC1OFR::NoOvercapture
235    }
236    ///The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
237    #[inline(always)]
238    pub fn is_overcapture(&self) -> bool {
239        *self == CC1OFR::Overcapture
240    }
241}
242/**Capture/Compare %s overcapture flag
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum CC1OFW {
248    ///0: Clear flag
249    Clear = 0,
250}
251impl From<CC1OFW> for bool {
252    #[inline(always)]
253    fn from(variant: CC1OFW) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `CCOF(1-2)` writer - Capture/Compare %s overcapture flag
258pub type CCOF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1OFW>;
259impl<'a, REG> CCOF_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    ///Clear flag
264    #[inline(always)]
265    pub fn clear(self) -> &'a mut crate::W<REG> {
266        self.variant(CC1OFW::Clear)
267    }
268}
269impl R {
270    ///Bit 0 - Update interrupt flag
271    #[inline(always)]
272    pub fn uif(&self) -> UIF_R {
273        UIF_R::new((self.bits & 1) != 0)
274    }
275    ///Capture/compare (1-2) interrupt flag
276    ///
277    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
278    #[inline(always)]
279    pub fn ccif(&self, n: u8) -> CCIF_R {
280        #[allow(clippy::no_effect)] [(); 2][n as usize];
281        CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0)
282    }
283    ///Iterator for array of:
284    ///Capture/compare (1-2) interrupt flag
285    #[inline(always)]
286    pub fn ccif_iter(&self) -> impl Iterator<Item = CCIF_R> + '_ {
287        (0..2).map(move |n| CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0))
288    }
289    ///Bit 1 - Capture/compare 1 interrupt flag
290    #[inline(always)]
291    pub fn cc1if(&self) -> CCIF_R {
292        CCIF_R::new(((self.bits >> 1) & 1) != 0)
293    }
294    ///Bit 2 - Capture/compare 2 interrupt flag
295    #[inline(always)]
296    pub fn cc2if(&self) -> CCIF_R {
297        CCIF_R::new(((self.bits >> 2) & 1) != 0)
298    }
299    ///Bit 6 - Trigger interrupt flag
300    #[inline(always)]
301    pub fn tif(&self) -> TIF_R {
302        TIF_R::new(((self.bits >> 6) & 1) != 0)
303    }
304    ///Capture/Compare (1-2) overcapture flag
305    ///
306    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
307    #[inline(always)]
308    pub fn ccof(&self, n: u8) -> CCOF_R {
309        #[allow(clippy::no_effect)] [(); 2][n as usize];
310        CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0)
311    }
312    ///Iterator for array of:
313    ///Capture/Compare (1-2) overcapture flag
314    #[inline(always)]
315    pub fn ccof_iter(&self) -> impl Iterator<Item = CCOF_R> + '_ {
316        (0..2).map(move |n| CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0))
317    }
318    ///Bit 9 - Capture/Compare 1 overcapture flag
319    #[inline(always)]
320    pub fn cc1of(&self) -> CCOF_R {
321        CCOF_R::new(((self.bits >> 9) & 1) != 0)
322    }
323    ///Bit 10 - Capture/Compare 2 overcapture flag
324    #[inline(always)]
325    pub fn cc2of(&self) -> CCOF_R {
326        CCOF_R::new(((self.bits >> 10) & 1) != 0)
327    }
328}
329impl core::fmt::Debug for R {
330    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
331        f.debug_struct("SR")
332            .field("cc1of", &self.cc1of())
333            .field("cc2of", &self.cc2of())
334            .field("tif", &self.tif())
335            .field("cc1if", &self.cc1if())
336            .field("cc2if", &self.cc2if())
337            .field("uif", &self.uif())
338            .finish()
339    }
340}
341impl W {
342    ///Bit 0 - Update interrupt flag
343    #[inline(always)]
344    pub fn uif(&mut self) -> UIF_W<SRrs> {
345        UIF_W::new(self, 0)
346    }
347    ///Capture/compare (1-2) interrupt flag
348    ///
349    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
350    #[inline(always)]
351    pub fn ccif(&mut self, n: u8) -> CCIF_W<SRrs> {
352        #[allow(clippy::no_effect)] [(); 2][n as usize];
353        CCIF_W::new(self, n + 1)
354    }
355    ///Bit 1 - Capture/compare 1 interrupt flag
356    #[inline(always)]
357    pub fn cc1if(&mut self) -> CCIF_W<SRrs> {
358        CCIF_W::new(self, 1)
359    }
360    ///Bit 2 - Capture/compare 2 interrupt flag
361    #[inline(always)]
362    pub fn cc2if(&mut self) -> CCIF_W<SRrs> {
363        CCIF_W::new(self, 2)
364    }
365    ///Bit 6 - Trigger interrupt flag
366    #[inline(always)]
367    pub fn tif(&mut self) -> TIF_W<SRrs> {
368        TIF_W::new(self, 6)
369    }
370    ///Capture/Compare (1-2) overcapture flag
371    ///
372    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
373    #[inline(always)]
374    pub fn ccof(&mut self, n: u8) -> CCOF_W<SRrs> {
375        #[allow(clippy::no_effect)] [(); 2][n as usize];
376        CCOF_W::new(self, n + 9)
377    }
378    ///Bit 9 - Capture/Compare 1 overcapture flag
379    #[inline(always)]
380    pub fn cc1of(&mut self) -> CCOF_W<SRrs> {
381        CCOF_W::new(self, 9)
382    }
383    ///Bit 10 - Capture/Compare 2 overcapture flag
384    #[inline(always)]
385    pub fn cc2of(&mut self) -> CCOF_W<SRrs> {
386        CCOF_W::new(self, 10)
387    }
388}
389/**status register
390
391You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
392
393See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM9:SR)*/
394pub struct SRrs;
395impl crate::RegisterSpec for SRrs {
396    type Ux = u32;
397}
398///`read()` method returns [`sr::R`](R) reader structure
399impl crate::Readable for SRrs {}
400///`write(|w| ..)` method takes [`sr::W`](W) writer structure
401impl crate::Writable for SRrs {
402    type Safety = crate::Unsafe;
403    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0647;
404}
405///`reset()` method sets SR to value 0
406impl crate::Resettable for SRrs {}
stm32f1_staging/stm32f101/tim9/sr.rs

stm32f1_staging/stm32f101/tim9/
sr.rs
