stm32f1_staging/stm32f101/tim6/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**Counter enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CEN {
11    ///0: Counter disabled
12    Disabled = 0,
13    ///1: Counter enabled
14    Enabled = 1,
15}
16impl From<CEN> for bool {
17    #[inline(always)]
18    fn from(variant: CEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CEN` reader - Counter enable
23pub type CEN_R = crate::BitReader<CEN>;
24impl CEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CEN {
28        match self.bits {
29            false => CEN::Disabled,
30            true => CEN::Enabled,
31        }
32    }
33    ///Counter disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CEN::Disabled
37    }
38    ///Counter enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CEN::Enabled
42    }
43}
44///Field `CEN` writer - Counter enable
45pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG, CEN>;
46impl<'a, REG> CEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Counter disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CEN::Disabled)
54    }
55    ///Counter enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CEN::Enabled)
59    }
60}
61/**Update disable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum UDIS {
67    ///0: Update event enabled
68    Enabled = 0,
69    ///1: Update event disabled
70    Disabled = 1,
71}
72impl From<UDIS> for bool {
73    #[inline(always)]
74    fn from(variant: UDIS) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `UDIS` reader - Update disable
79pub type UDIS_R = crate::BitReader<UDIS>;
80impl UDIS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> UDIS {
84        match self.bits {
85            false => UDIS::Enabled,
86            true => UDIS::Disabled,
87        }
88    }
89    ///Update event enabled
90    #[inline(always)]
91    pub fn is_enabled(&self) -> bool {
92        *self == UDIS::Enabled
93    }
94    ///Update event disabled
95    #[inline(always)]
96    pub fn is_disabled(&self) -> bool {
97        *self == UDIS::Disabled
98    }
99}
100///Field `UDIS` writer - Update disable
101pub type UDIS_W<'a, REG> = crate::BitWriter<'a, REG, UDIS>;
102impl<'a, REG> UDIS_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Update event enabled
107    #[inline(always)]
108    pub fn enabled(self) -> &'a mut crate::W<REG> {
109        self.variant(UDIS::Enabled)
110    }
111    ///Update event disabled
112    #[inline(always)]
113    pub fn disabled(self) -> &'a mut crate::W<REG> {
114        self.variant(UDIS::Disabled)
115    }
116}
117/**Update request source
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum URS {
123    ///0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
124    AnyEvent = 0,
125    ///1: Only counter overflow/underflow generates an update interrupt or DMA request
126    CounterOnly = 1,
127}
128impl From<URS> for bool {
129    #[inline(always)]
130    fn from(variant: URS) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `URS` reader - Update request source
135pub type URS_R = crate::BitReader<URS>;
136impl URS_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> URS {
140        match self.bits {
141            false => URS::AnyEvent,
142            true => URS::CounterOnly,
143        }
144    }
145    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
146    #[inline(always)]
147    pub fn is_any_event(&self) -> bool {
148        *self == URS::AnyEvent
149    }
150    ///Only counter overflow/underflow generates an update interrupt or DMA request
151    #[inline(always)]
152    pub fn is_counter_only(&self) -> bool {
153        *self == URS::CounterOnly
154    }
155}
156///Field `URS` writer - Update request source
157pub type URS_W<'a, REG> = crate::BitWriter<'a, REG, URS>;
158impl<'a, REG> URS_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
163    #[inline(always)]
164    pub fn any_event(self) -> &'a mut crate::W<REG> {
165        self.variant(URS::AnyEvent)
166    }
167    ///Only counter overflow/underflow generates an update interrupt or DMA request
168    #[inline(always)]
169    pub fn counter_only(self) -> &'a mut crate::W<REG> {
170        self.variant(URS::CounterOnly)
171    }
172}
173/**One-pulse mode
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum OPM {
179    ///0: Counter is not stopped at update event
180    Disabled = 0,
181    ///1: Counter stops counting at the next update event (clearing the CEN bit)
182    Enabled = 1,
183}
184impl From<OPM> for bool {
185    #[inline(always)]
186    fn from(variant: OPM) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `OPM` reader - One-pulse mode
191pub type OPM_R = crate::BitReader<OPM>;
192impl OPM_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> OPM {
196        match self.bits {
197            false => OPM::Disabled,
198            true => OPM::Enabled,
199        }
200    }
201    ///Counter is not stopped at update event
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == OPM::Disabled
205    }
206    ///Counter stops counting at the next update event (clearing the CEN bit)
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == OPM::Enabled
210    }
211}
212///Field `OPM` writer - One-pulse mode
213pub type OPM_W<'a, REG> = crate::BitWriter<'a, REG, OPM>;
214impl<'a, REG> OPM_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Counter is not stopped at update event
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(OPM::Disabled)
222    }
223    ///Counter stops counting at the next update event (clearing the CEN bit)
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(OPM::Enabled)
227    }
228}
229/**Auto-reload preload enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum ARPE {
235    ///0: TIMx_APRR register is not buffered
236    Disabled = 0,
237    ///1: TIMx_APRR register is buffered
238    Enabled = 1,
239}
240impl From<ARPE> for bool {
241    #[inline(always)]
242    fn from(variant: ARPE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `ARPE` reader - Auto-reload preload enable
247pub type ARPE_R = crate::BitReader<ARPE>;
248impl ARPE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> ARPE {
252        match self.bits {
253            false => ARPE::Disabled,
254            true => ARPE::Enabled,
255        }
256    }
257    ///TIMx_APRR register is not buffered
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == ARPE::Disabled
261    }
262    ///TIMx_APRR register is buffered
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == ARPE::Enabled
266    }
267}
268///Field `ARPE` writer - Auto-reload preload enable
269pub type ARPE_W<'a, REG> = crate::BitWriter<'a, REG, ARPE>;
270impl<'a, REG> ARPE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///TIMx_APRR register is not buffered
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(ARPE::Disabled)
278    }
279    ///TIMx_APRR register is buffered
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(ARPE::Enabled)
283    }
284}
285impl R {
286    ///Bit 0 - Counter enable
287    #[inline(always)]
288    pub fn cen(&self) -> CEN_R {
289        CEN_R::new((self.bits & 1) != 0)
290    }
291    ///Bit 1 - Update disable
292    #[inline(always)]
293    pub fn udis(&self) -> UDIS_R {
294        UDIS_R::new(((self.bits >> 1) & 1) != 0)
295    }
296    ///Bit 2 - Update request source
297    #[inline(always)]
298    pub fn urs(&self) -> URS_R {
299        URS_R::new(((self.bits >> 2) & 1) != 0)
300    }
301    ///Bit 3 - One-pulse mode
302    #[inline(always)]
303    pub fn opm(&self) -> OPM_R {
304        OPM_R::new(((self.bits >> 3) & 1) != 0)
305    }
306    ///Bit 7 - Auto-reload preload enable
307    #[inline(always)]
308    pub fn arpe(&self) -> ARPE_R {
309        ARPE_R::new(((self.bits >> 7) & 1) != 0)
310    }
311}
312impl core::fmt::Debug for R {
313    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
314        f.debug_struct("CR1")
315            .field("arpe", &self.arpe())
316            .field("opm", &self.opm())
317            .field("urs", &self.urs())
318            .field("udis", &self.udis())
319            .field("cen", &self.cen())
320            .finish()
321    }
322}
323impl W {
324    ///Bit 0 - Counter enable
325    #[inline(always)]
326    pub fn cen(&mut self) -> CEN_W<CR1rs> {
327        CEN_W::new(self, 0)
328    }
329    ///Bit 1 - Update disable
330    #[inline(always)]
331    pub fn udis(&mut self) -> UDIS_W<CR1rs> {
332        UDIS_W::new(self, 1)
333    }
334    ///Bit 2 - Update request source
335    #[inline(always)]
336    pub fn urs(&mut self) -> URS_W<CR1rs> {
337        URS_W::new(self, 2)
338    }
339    ///Bit 3 - One-pulse mode
340    #[inline(always)]
341    pub fn opm(&mut self) -> OPM_W<CR1rs> {
342        OPM_W::new(self, 3)
343    }
344    ///Bit 7 - Auto-reload preload enable
345    #[inline(always)]
346    pub fn arpe(&mut self) -> ARPE_W<CR1rs> {
347        ARPE_W::new(self, 7)
348    }
349}
350/**control register 1
351
352You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
353
354See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:CR1)*/
355pub struct CR1rs;
356impl crate::RegisterSpec for CR1rs {
357    type Ux = u32;
358}
359///`read()` method returns [`cr1::R`](R) reader structure
360impl crate::Readable for CR1rs {}
361///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
362impl crate::Writable for CR1rs {
363    type Safety = crate::Unsafe;
364}
365///`reset()` method sets CR1 to value 0
366impl crate::Resettable for CR1rs {}
stm32f1_staging/stm32f101/tim6/cr1.rs

stm32f1_staging/stm32f101/tim6/
cr1.rs
