stm32f1_staging/stm32f101/tim10/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Update interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIFR {
11    ///0: No update occurred
12    NoUpdateOccurred = 0,
13    ///1: Update interrupt pending
14    UpdatePending = 1,
15}
16impl From<UIFR> for bool {
17    #[inline(always)]
18    fn from(variant: UIFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIF` reader - Update interrupt flag
23pub type UIF_R = crate::BitReader<UIFR>;
24impl UIF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIFR {
28        match self.bits {
29            false => UIFR::NoUpdateOccurred,
30            true => UIFR::UpdatePending,
31        }
32    }
33    ///No update occurred
34    #[inline(always)]
35    pub fn is_no_update_occurred(&self) -> bool {
36        *self == UIFR::NoUpdateOccurred
37    }
38    ///Update interrupt pending
39    #[inline(always)]
40    pub fn is_update_pending(&self) -> bool {
41        *self == UIFR::UpdatePending
42    }
43}
44/**Update interrupt flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum UIFW {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<UIFW> for bool {
54    #[inline(always)]
55    fn from(variant: UIFW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `UIF` writer - Update interrupt flag
60pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
61impl<'a, REG> UIF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(UIFW::Clear)
69    }
70}
71/**Capture/compare %s interrupt flag
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum CC1IFR {
77    ///0: No campture/compare has been detected
78    NoMatch = 0,
79    ///1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
80    Match = 1,
81}
82impl From<CC1IFR> for bool {
83    #[inline(always)]
84    fn from(variant: CC1IFR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `CCIF(1-1)` reader - Capture/compare %s interrupt flag
89pub type CCIF_R = crate::BitReader<CC1IFR>;
90impl CCIF_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> CC1IFR {
94        match self.bits {
95            false => CC1IFR::NoMatch,
96            true => CC1IFR::Match,
97        }
98    }
99    ///No campture/compare has been detected
100    #[inline(always)]
101    pub fn is_no_match(&self) -> bool {
102        *self == CC1IFR::NoMatch
103    }
104    ///If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
105    #[inline(always)]
106    pub fn is_match(&self) -> bool {
107        *self == CC1IFR::Match
108    }
109}
110/**Capture/compare %s interrupt flag
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CC1IFW {
116    ///0: Clear flag
117    Clear = 0,
118}
119impl From<CC1IFW> for bool {
120    #[inline(always)]
121    fn from(variant: CC1IFW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `CCIF(1-1)` writer - Capture/compare %s interrupt flag
126pub type CCIF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1IFW>;
127impl<'a, REG> CCIF_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(CC1IFW::Clear)
135    }
136}
137/**Capture/Compare %s overcapture flag
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum CC1OFR {
143    ///0: No overcapture has been detected
144    NoOvercapture = 0,
145    ///1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
146    Overcapture = 1,
147}
148impl From<CC1OFR> for bool {
149    #[inline(always)]
150    fn from(variant: CC1OFR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `CCOF(1-1)` reader - Capture/Compare %s overcapture flag
155pub type CCOF_R = crate::BitReader<CC1OFR>;
156impl CCOF_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> CC1OFR {
160        match self.bits {
161            false => CC1OFR::NoOvercapture,
162            true => CC1OFR::Overcapture,
163        }
164    }
165    ///No overcapture has been detected
166    #[inline(always)]
167    pub fn is_no_overcapture(&self) -> bool {
168        *self == CC1OFR::NoOvercapture
169    }
170    ///The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
171    #[inline(always)]
172    pub fn is_overcapture(&self) -> bool {
173        *self == CC1OFR::Overcapture
174    }
175}
176/**Capture/Compare %s overcapture flag
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum CC1OFW {
182    ///0: Clear flag
183    Clear = 0,
184}
185impl From<CC1OFW> for bool {
186    #[inline(always)]
187    fn from(variant: CC1OFW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `CCOF(1-1)` writer - Capture/Compare %s overcapture flag
192pub type CCOF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1OFW>;
193impl<'a, REG> CCOF_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(CC1OFW::Clear)
201    }
202}
203impl R {
204    ///Bit 0 - Update interrupt flag
205    #[inline(always)]
206    pub fn uif(&self) -> UIF_R {
207        UIF_R::new((self.bits & 1) != 0)
208    }
209    ///Capture/compare (1-1) interrupt flag
210    ///
211    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
212    #[inline(always)]
213    pub fn ccif(&self, n: u8) -> CCIF_R {
214        #[allow(clippy::no_effect)] [(); 1][n as usize];
215        CCIF_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
216    }
217    ///Iterator for array of:
218    ///Capture/compare (1-1) interrupt flag
219    #[inline(always)]
220    pub fn ccif_iter(&self) -> impl Iterator<Item = CCIF_R> + '_ {
221        (0..1).map(move |n| CCIF_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
222    }
223    ///Bit 1 - Capture/compare 1 interrupt flag
224    #[inline(always)]
225    pub fn cc1if(&self) -> CCIF_R {
226        CCIF_R::new(((self.bits >> 1) & 1) != 0)
227    }
228    ///Capture/Compare (1-1) overcapture flag
229    ///
230    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
231    #[inline(always)]
232    pub fn ccof(&self, n: u8) -> CCOF_R {
233        #[allow(clippy::no_effect)] [(); 1][n as usize];
234        CCOF_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0)
235    }
236    ///Iterator for array of:
237    ///Capture/Compare (1-1) overcapture flag
238    #[inline(always)]
239    pub fn ccof_iter(&self) -> impl Iterator<Item = CCOF_R> + '_ {
240        (0..1).map(move |n| CCOF_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0))
241    }
242    ///Bit 9 - Capture/Compare 1 overcapture flag
243    #[inline(always)]
244    pub fn cc1of(&self) -> CCOF_R {
245        CCOF_R::new(((self.bits >> 9) & 1) != 0)
246    }
247}
248impl core::fmt::Debug for R {
249    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
250        f.debug_struct("SR")
251            .field("cc1of", &self.cc1of())
252            .field("cc1if", &self.cc1if())
253            .field("uif", &self.uif())
254            .finish()
255    }
256}
257impl W {
258    ///Bit 0 - Update interrupt flag
259    #[inline(always)]
260    pub fn uif(&mut self) -> UIF_W<SRrs> {
261        UIF_W::new(self, 0)
262    }
263    ///Capture/compare (1-1) interrupt flag
264    ///
265    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
266    #[inline(always)]
267    pub fn ccif(&mut self, n: u8) -> CCIF_W<SRrs> {
268        #[allow(clippy::no_effect)] [(); 1][n as usize];
269        CCIF_W::new(self, n * 0 + 1)
270    }
271    ///Bit 1 - Capture/compare 1 interrupt flag
272    #[inline(always)]
273    pub fn cc1if(&mut self) -> CCIF_W<SRrs> {
274        CCIF_W::new(self, 1)
275    }
276    ///Capture/Compare (1-1) overcapture flag
277    ///
278    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
279    #[inline(always)]
280    pub fn ccof(&mut self, n: u8) -> CCOF_W<SRrs> {
281        #[allow(clippy::no_effect)] [(); 1][n as usize];
282        CCOF_W::new(self, n * 0 + 9)
283    }
284    ///Bit 9 - Capture/Compare 1 overcapture flag
285    #[inline(always)]
286    pub fn cc1of(&mut self) -> CCOF_W<SRrs> {
287        CCOF_W::new(self, 9)
288    }
289}
290/**status register
291
292You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:SR)*/
295pub struct SRrs;
296impl crate::RegisterSpec for SRrs {
297    type Ux = u32;
298}
299///`read()` method returns [`sr::R`](R) reader structure
300impl crate::Readable for SRrs {}
301///`write(|w| ..)` method takes [`sr::W`](W) writer structure
302impl crate::Writable for SRrs {
303    type Safety = crate::Unsafe;
304    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0203;
305}
306///`reset()` method sets SR to value 0
307impl crate::Resettable for SRrs {}
stm32f1_staging/stm32f101/tim10/sr.rs

stm32f1_staging/stm32f101/tim10/
sr.rs
