stm32f1_staging/stm32f101/tim10/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-1)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-1)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-1)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-1)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117///Field `CCNP(1-1)` reader - Capture/Compare %s output Polarity
118pub type CCNP_R = crate::BitReader;
119///Field `CCNP(1-1)` writer - Capture/Compare %s output Polarity
120pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG>;
121impl R {
122    ///Capture/Compare (1-1) output enable
123    ///
124    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
125    #[inline(always)]
126    pub fn cce(&self, n: u8) -> CCE_R {
127        #[allow(clippy::no_effect)] [(); 1][n as usize];
128        CCE_R::new(((self.bits >> (n * 0)) & 1) != 0)
129    }
130    ///Iterator for array of:
131    ///Capture/Compare (1-1) output enable
132    #[inline(always)]
133    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
134        (0..1).map(move |n| CCE_R::new(((self.bits >> (n * 0)) & 1) != 0))
135    }
136    ///Bit 0 - Capture/Compare 1 output enable
137    #[inline(always)]
138    pub fn cc1e(&self) -> CCE_R {
139        CCE_R::new((self.bits & 1) != 0)
140    }
141    ///Capture/Compare (1-1) output Polarity
142    ///
143    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
144    #[inline(always)]
145    pub fn ccp(&self, n: u8) -> CCP_R {
146        #[allow(clippy::no_effect)] [(); 1][n as usize];
147        CCP_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
148    }
149    ///Iterator for array of:
150    ///Capture/Compare (1-1) output Polarity
151    #[inline(always)]
152    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
153        (0..1).map(move |n| CCP_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
154    }
155    ///Bit 1 - Capture/Compare 1 output Polarity
156    #[inline(always)]
157    pub fn cc1p(&self) -> CCP_R {
158        CCP_R::new(((self.bits >> 1) & 1) != 0)
159    }
160    ///Capture/Compare (1-1) output Polarity
161    ///
162    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
163    #[inline(always)]
164    pub fn ccnp(&self, n: u8) -> CCNP_R {
165        #[allow(clippy::no_effect)] [(); 1][n as usize];
166        CCNP_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0)
167    }
168    ///Iterator for array of:
169    ///Capture/Compare (1-1) output Polarity
170    #[inline(always)]
171    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
172        (0..1).map(move |n| CCNP_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0))
173    }
174    ///Bit 3 - Capture/Compare 1 output Polarity
175    #[inline(always)]
176    pub fn cc1np(&self) -> CCNP_R {
177        CCNP_R::new(((self.bits >> 3) & 1) != 0)
178    }
179}
180impl core::fmt::Debug for R {
181    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
182        f.debug_struct("CCER")
183            .field("cc1np", &self.cc1np())
184            .field("cc1p", &self.cc1p())
185            .field("cc1e", &self.cc1e())
186            .finish()
187    }
188}
189impl W {
190    ///Capture/Compare (1-1) output enable
191    ///
192    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
193    #[inline(always)]
194    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
195        #[allow(clippy::no_effect)] [(); 1][n as usize];
196        CCE_W::new(self, n * 0)
197    }
198    ///Bit 0 - Capture/Compare 1 output enable
199    #[inline(always)]
200    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
201        CCE_W::new(self, 0)
202    }
203    ///Capture/Compare (1-1) output Polarity
204    ///
205    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
206    #[inline(always)]
207    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
208        #[allow(clippy::no_effect)] [(); 1][n as usize];
209        CCP_W::new(self, n * 0 + 1)
210    }
211    ///Bit 1 - Capture/Compare 1 output Polarity
212    #[inline(always)]
213    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
214        CCP_W::new(self, 1)
215    }
216    ///Capture/Compare (1-1) output Polarity
217    ///
218    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
219    #[inline(always)]
220    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
221        #[allow(clippy::no_effect)] [(); 1][n as usize];
222        CCNP_W::new(self, n * 0 + 3)
223    }
224    ///Bit 3 - Capture/Compare 1 output Polarity
225    #[inline(always)]
226    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
227        CCNP_W::new(self, 3)
228    }
229}
230/**capture/compare enable register
231
232You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CCER)*/
235pub struct CCERrs;
236impl crate::RegisterSpec for CCERrs {
237    type Ux = u32;
238}
239///`read()` method returns [`ccer::R`](R) reader structure
240impl crate::Readable for CCERrs {}
241///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
242impl crate::Writable for CCERrs {
243    type Safety = crate::Unsafe;
244}
245///`reset()` method sets CCER to value 0
246impl crate::Resettable for CCERrs {}
stm32f1_staging/stm32f101/tim10/ccer.rs

stm32f1_staging/stm32f101/tim10/
ccer.rs
