stm32f1_staging/stm32f101/rcc/
cir.rs

1///Register `CIR` reader
2pub type R = crate::R<CIRrs>;
3///Register `CIR` writer
4pub type W = crate::W<CIRrs>;
5/**LSI Ready Interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LSIRDYFR {
11    ///0: No clock ready interrupt
12    NotInterrupted = 0,
13    ///1: Clock ready interrupt
14    Interrupted = 1,
15}
16impl From<LSIRDYFR> for bool {
17    #[inline(always)]
18    fn from(variant: LSIRDYFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LSIRDYF` reader - LSI Ready Interrupt flag
23pub type LSIRDYF_R = crate::BitReader<LSIRDYFR>;
24impl LSIRDYF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LSIRDYFR {
28        match self.bits {
29            false => LSIRDYFR::NotInterrupted,
30            true => LSIRDYFR::Interrupted,
31        }
32    }
33    ///No clock ready interrupt
34    #[inline(always)]
35    pub fn is_not_interrupted(&self) -> bool {
36        *self == LSIRDYFR::NotInterrupted
37    }
38    ///Clock ready interrupt
39    #[inline(always)]
40    pub fn is_interrupted(&self) -> bool {
41        *self == LSIRDYFR::Interrupted
42    }
43}
44///Field `LSERDYF` reader - LSE Ready Interrupt flag
45pub use LSIRDYF_R as LSERDYF_R;
46///Field `HSIRDYF` reader - HSI Ready Interrupt flag
47pub use LSIRDYF_R as HSIRDYF_R;
48///Field `HSERDYF` reader - HSE Ready Interrupt flag
49pub use LSIRDYF_R as HSERDYF_R;
50///Field `PLLRDYF` reader - PLL Ready Interrupt flag
51pub use LSIRDYF_R as PLLRDYF_R;
52/**Clock Security System Interrupt flag
53
54Value on reset: 0*/
55#[cfg_attr(feature = "defmt", derive(defmt::Format))]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57pub enum CSSFR {
58    ///0: No clock security interrupt caused by HSE clock failure
59    NotInterrupted = 0,
60    ///1: Clock security interrupt caused by HSE clock failure
61    Interrupted = 1,
62}
63impl From<CSSFR> for bool {
64    #[inline(always)]
65    fn from(variant: CSSFR) -> Self {
66        variant as u8 != 0
67    }
68}
69///Field `CSSF` reader - Clock Security System Interrupt flag
70pub type CSSF_R = crate::BitReader<CSSFR>;
71impl CSSF_R {
72    ///Get enumerated values variant
73    #[inline(always)]
74    pub const fn variant(&self) -> CSSFR {
75        match self.bits {
76            false => CSSFR::NotInterrupted,
77            true => CSSFR::Interrupted,
78        }
79    }
80    ///No clock security interrupt caused by HSE clock failure
81    #[inline(always)]
82    pub fn is_not_interrupted(&self) -> bool {
83        *self == CSSFR::NotInterrupted
84    }
85    ///Clock security interrupt caused by HSE clock failure
86    #[inline(always)]
87    pub fn is_interrupted(&self) -> bool {
88        *self == CSSFR::Interrupted
89    }
90}
91/**LSI Ready Interrupt Enable
92
93Value on reset: 0*/
94#[cfg_attr(feature = "defmt", derive(defmt::Format))]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum LSIRDYIE {
97    ///0: Interrupt disabled
98    Disabled = 0,
99    ///1: Interrupt enabled
100    Enabled = 1,
101}
102impl From<LSIRDYIE> for bool {
103    #[inline(always)]
104    fn from(variant: LSIRDYIE) -> Self {
105        variant as u8 != 0
106    }
107}
108///Field `LSIRDYIE` reader - LSI Ready Interrupt Enable
109pub type LSIRDYIE_R = crate::BitReader<LSIRDYIE>;
110impl LSIRDYIE_R {
111    ///Get enumerated values variant
112    #[inline(always)]
113    pub const fn variant(&self) -> LSIRDYIE {
114        match self.bits {
115            false => LSIRDYIE::Disabled,
116            true => LSIRDYIE::Enabled,
117        }
118    }
119    ///Interrupt disabled
120    #[inline(always)]
121    pub fn is_disabled(&self) -> bool {
122        *self == LSIRDYIE::Disabled
123    }
124    ///Interrupt enabled
125    #[inline(always)]
126    pub fn is_enabled(&self) -> bool {
127        *self == LSIRDYIE::Enabled
128    }
129}
130///Field `LSIRDYIE` writer - LSI Ready Interrupt Enable
131pub type LSIRDYIE_W<'a, REG> = crate::BitWriter<'a, REG, LSIRDYIE>;
132impl<'a, REG> LSIRDYIE_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135{
136    ///Interrupt disabled
137    #[inline(always)]
138    pub fn disabled(self) -> &'a mut crate::W<REG> {
139        self.variant(LSIRDYIE::Disabled)
140    }
141    ///Interrupt enabled
142    #[inline(always)]
143    pub fn enabled(self) -> &'a mut crate::W<REG> {
144        self.variant(LSIRDYIE::Enabled)
145    }
146}
147///Field `LSERDYIE` reader - LSE Ready Interrupt Enable
148pub use LSIRDYIE_R as LSERDYIE_R;
149///Field `HSIRDYIE` reader - HSI Ready Interrupt Enable
150pub use LSIRDYIE_R as HSIRDYIE_R;
151///Field `HSERDYIE` reader - HSE Ready Interrupt Enable
152pub use LSIRDYIE_R as HSERDYIE_R;
153///Field `PLLRDYIE` reader - PLL Ready Interrupt Enable
154pub use LSIRDYIE_R as PLLRDYIE_R;
155///Field `LSERDYIE` writer - LSE Ready Interrupt Enable
156pub use LSIRDYIE_W as LSERDYIE_W;
157///Field `HSIRDYIE` writer - HSI Ready Interrupt Enable
158pub use LSIRDYIE_W as HSIRDYIE_W;
159///Field `HSERDYIE` writer - HSE Ready Interrupt Enable
160pub use LSIRDYIE_W as HSERDYIE_W;
161///Field `PLLRDYIE` writer - PLL Ready Interrupt Enable
162pub use LSIRDYIE_W as PLLRDYIE_W;
163/**LSI Ready Interrupt Clear
164
165Value on reset: 0*/
166#[cfg_attr(feature = "defmt", derive(defmt::Format))]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum LSIRDYCW {
169    ///1: Clear interrupt flag
170    Clear = 1,
171}
172impl From<LSIRDYCW> for bool {
173    #[inline(always)]
174    fn from(variant: LSIRDYCW) -> Self {
175        variant as u8 != 0
176    }
177}
178///Field `LSIRDYC` writer - LSI Ready Interrupt Clear
179pub type LSIRDYC_W<'a, REG> = crate::BitWriter<'a, REG, LSIRDYCW>;
180impl<'a, REG> LSIRDYC_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    ///Clear interrupt flag
185    #[inline(always)]
186    pub fn clear(self) -> &'a mut crate::W<REG> {
187        self.variant(LSIRDYCW::Clear)
188    }
189}
190///Field `LSERDYC` writer - LSE Ready Interrupt Clear
191pub use LSIRDYC_W as LSERDYC_W;
192///Field `HSIRDYC` writer - HSI Ready Interrupt Clear
193pub use LSIRDYC_W as HSIRDYC_W;
194///Field `HSERDYC` writer - HSE Ready Interrupt Clear
195pub use LSIRDYC_W as HSERDYC_W;
196///Field `PLLRDYC` writer - PLL Ready Interrupt Clear
197pub use LSIRDYC_W as PLLRDYC_W;
198/**Clock security system interrupt clear
199
200Value on reset: 0*/
201#[cfg_attr(feature = "defmt", derive(defmt::Format))]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203pub enum CSSCW {
204    ///1: Clear CSSF flag
205    Clear = 1,
206}
207impl From<CSSCW> for bool {
208    #[inline(always)]
209    fn from(variant: CSSCW) -> Self {
210        variant as u8 != 0
211    }
212}
213///Field `CSSC` writer - Clock security system interrupt clear
214pub type CSSC_W<'a, REG> = crate::BitWriter<'a, REG, CSSCW>;
215impl<'a, REG> CSSC_W<'a, REG>
216where
217    REG: crate::Writable + crate::RegisterSpec,
218{
219    ///Clear CSSF flag
220    #[inline(always)]
221    pub fn clear(self) -> &'a mut crate::W<REG> {
222        self.variant(CSSCW::Clear)
223    }
224}
225impl R {
226    ///Bit 0 - LSI Ready Interrupt flag
227    #[inline(always)]
228    pub fn lsirdyf(&self) -> LSIRDYF_R {
229        LSIRDYF_R::new((self.bits & 1) != 0)
230    }
231    ///Bit 1 - LSE Ready Interrupt flag
232    #[inline(always)]
233    pub fn lserdyf(&self) -> LSERDYF_R {
234        LSERDYF_R::new(((self.bits >> 1) & 1) != 0)
235    }
236    ///Bit 2 - HSI Ready Interrupt flag
237    #[inline(always)]
238    pub fn hsirdyf(&self) -> HSIRDYF_R {
239        HSIRDYF_R::new(((self.bits >> 2) & 1) != 0)
240    }
241    ///Bit 3 - HSE Ready Interrupt flag
242    #[inline(always)]
243    pub fn hserdyf(&self) -> HSERDYF_R {
244        HSERDYF_R::new(((self.bits >> 3) & 1) != 0)
245    }
246    ///Bit 4 - PLL Ready Interrupt flag
247    #[inline(always)]
248    pub fn pllrdyf(&self) -> PLLRDYF_R {
249        PLLRDYF_R::new(((self.bits >> 4) & 1) != 0)
250    }
251    ///Bit 7 - Clock Security System Interrupt flag
252    #[inline(always)]
253    pub fn cssf(&self) -> CSSF_R {
254        CSSF_R::new(((self.bits >> 7) & 1) != 0)
255    }
256    ///Bit 8 - LSI Ready Interrupt Enable
257    #[inline(always)]
258    pub fn lsirdyie(&self) -> LSIRDYIE_R {
259        LSIRDYIE_R::new(((self.bits >> 8) & 1) != 0)
260    }
261    ///Bit 9 - LSE Ready Interrupt Enable
262    #[inline(always)]
263    pub fn lserdyie(&self) -> LSERDYIE_R {
264        LSERDYIE_R::new(((self.bits >> 9) & 1) != 0)
265    }
266    ///Bit 10 - HSI Ready Interrupt Enable
267    #[inline(always)]
268    pub fn hsirdyie(&self) -> HSIRDYIE_R {
269        HSIRDYIE_R::new(((self.bits >> 10) & 1) != 0)
270    }
271    ///Bit 11 - HSE Ready Interrupt Enable
272    #[inline(always)]
273    pub fn hserdyie(&self) -> HSERDYIE_R {
274        HSERDYIE_R::new(((self.bits >> 11) & 1) != 0)
275    }
276    ///Bit 12 - PLL Ready Interrupt Enable
277    #[inline(always)]
278    pub fn pllrdyie(&self) -> PLLRDYIE_R {
279        PLLRDYIE_R::new(((self.bits >> 12) & 1) != 0)
280    }
281}
282impl core::fmt::Debug for R {
283    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
284        f.debug_struct("CIR")
285            .field("lsirdyf", &self.lsirdyf())
286            .field("lserdyf", &self.lserdyf())
287            .field("hsirdyf", &self.hsirdyf())
288            .field("hserdyf", &self.hserdyf())
289            .field("pllrdyf", &self.pllrdyf())
290            .field("cssf", &self.cssf())
291            .field("lsirdyie", &self.lsirdyie())
292            .field("lserdyie", &self.lserdyie())
293            .field("hsirdyie", &self.hsirdyie())
294            .field("hserdyie", &self.hserdyie())
295            .field("pllrdyie", &self.pllrdyie())
296            .finish()
297    }
298}
299impl W {
300    ///Bit 8 - LSI Ready Interrupt Enable
301    #[inline(always)]
302    pub fn lsirdyie(&mut self) -> LSIRDYIE_W<CIRrs> {
303        LSIRDYIE_W::new(self, 8)
304    }
305    ///Bit 9 - LSE Ready Interrupt Enable
306    #[inline(always)]
307    pub fn lserdyie(&mut self) -> LSERDYIE_W<CIRrs> {
308        LSERDYIE_W::new(self, 9)
309    }
310    ///Bit 10 - HSI Ready Interrupt Enable
311    #[inline(always)]
312    pub fn hsirdyie(&mut self) -> HSIRDYIE_W<CIRrs> {
313        HSIRDYIE_W::new(self, 10)
314    }
315    ///Bit 11 - HSE Ready Interrupt Enable
316    #[inline(always)]
317    pub fn hserdyie(&mut self) -> HSERDYIE_W<CIRrs> {
318        HSERDYIE_W::new(self, 11)
319    }
320    ///Bit 12 - PLL Ready Interrupt Enable
321    #[inline(always)]
322    pub fn pllrdyie(&mut self) -> PLLRDYIE_W<CIRrs> {
323        PLLRDYIE_W::new(self, 12)
324    }
325    ///Bit 16 - LSI Ready Interrupt Clear
326    #[inline(always)]
327    pub fn lsirdyc(&mut self) -> LSIRDYC_W<CIRrs> {
328        LSIRDYC_W::new(self, 16)
329    }
330    ///Bit 17 - LSE Ready Interrupt Clear
331    #[inline(always)]
332    pub fn lserdyc(&mut self) -> LSERDYC_W<CIRrs> {
333        LSERDYC_W::new(self, 17)
334    }
335    ///Bit 18 - HSI Ready Interrupt Clear
336    #[inline(always)]
337    pub fn hsirdyc(&mut self) -> HSIRDYC_W<CIRrs> {
338        HSIRDYC_W::new(self, 18)
339    }
340    ///Bit 19 - HSE Ready Interrupt Clear
341    #[inline(always)]
342    pub fn hserdyc(&mut self) -> HSERDYC_W<CIRrs> {
343        HSERDYC_W::new(self, 19)
344    }
345    ///Bit 20 - PLL Ready Interrupt Clear
346    #[inline(always)]
347    pub fn pllrdyc(&mut self) -> PLLRDYC_W<CIRrs> {
348        PLLRDYC_W::new(self, 20)
349    }
350    ///Bit 23 - Clock security system interrupt clear
351    #[inline(always)]
352    pub fn cssc(&mut self) -> CSSC_W<CIRrs> {
353        CSSC_W::new(self, 23)
354    }
355}
356/**Clock interrupt register (RCC_CIR)
357
358You can [`read`](crate::Reg::read) this register and get [`cir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
359
360See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#RCC:CIR)*/
361pub struct CIRrs;
362impl crate::RegisterSpec for CIRrs {
363    type Ux = u32;
364}
365///`read()` method returns [`cir::R`](R) reader structure
366impl crate::Readable for CIRrs {}
367///`write(|w| ..)` method takes [`cir::W`](W) writer structure
368impl crate::Writable for CIRrs {
369    type Safety = crate::Unsafe;
370}
371///`reset()` method sets CIR to value 0
372impl crate::Resettable for CIRrs {}
stm32f1_staging/stm32f101/rcc/cir.rs

stm32f1_staging/stm32f101/rcc/
cir.rs
