stm32f1_staging/stm32f101/rcc/
apb2rstr.rs

1///Register `APB2RSTR` reader
2pub type R = crate::R<APB2RSTRrs>;
3///Register `APB2RSTR` writer
4pub type W = crate::W<APB2RSTRrs>;
5/**Alternate function I/O reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIORST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<AFIORST> for bool {
15    #[inline(always)]
16    fn from(variant: AFIORST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `AFIORST` reader - Alternate function I/O reset
21pub type AFIORST_R = crate::BitReader<AFIORST>;
22impl AFIORST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<AFIORST> {
26        match self.bits {
27            true => Some(AFIORST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == AFIORST::Reset
35    }
36}
37///Field `AFIORST` writer - Alternate function I/O reset
38pub type AFIORST_W<'a, REG> = crate::BitWriter<'a, REG, AFIORST>;
39impl<'a, REG> AFIORST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(AFIORST::Reset)
47    }
48}
49///Field `IOPARST` reader - IO port A reset
50pub use AFIORST_R as IOPARST_R;
51///Field `IOPBRST` reader - IO port B reset
52pub use AFIORST_R as IOPBRST_R;
53///Field `IOPCRST` reader - IO port C reset
54pub use AFIORST_R as IOPCRST_R;
55///Field `IOPDRST` reader - IO port D reset
56pub use AFIORST_R as IOPDRST_R;
57///Field `IOPERST` reader - IO port E reset
58pub use AFIORST_R as IOPERST_R;
59///Field `IOPFRST` reader - IO port F reset
60pub use AFIORST_R as IOPFRST_R;
61///Field `IOPGRST` reader - IO port G reset
62pub use AFIORST_R as IOPGRST_R;
63///Field `ADC1RST` reader - ADC 1 interface reset
64pub use AFIORST_R as ADC1RST_R;
65///Field `SPI1RST` reader - SPI 1 reset
66pub use AFIORST_R as SPI1RST_R;
67///Field `USART1RST` reader - USART1 reset
68pub use AFIORST_R as USART1RST_R;
69///Field `TIM9RST` reader - TIM9 timer reset
70pub use AFIORST_R as TIM9RST_R;
71///Field `TIM10RST` reader - TIM10 timer reset
72pub use AFIORST_R as TIM10RST_R;
73///Field `TIM11RST` reader - TIM11 timer reset
74pub use AFIORST_R as TIM11RST_R;
75///Field `IOPARST` writer - IO port A reset
76pub use AFIORST_W as IOPARST_W;
77///Field `IOPBRST` writer - IO port B reset
78pub use AFIORST_W as IOPBRST_W;
79///Field `IOPCRST` writer - IO port C reset
80pub use AFIORST_W as IOPCRST_W;
81///Field `IOPDRST` writer - IO port D reset
82pub use AFIORST_W as IOPDRST_W;
83///Field `IOPERST` writer - IO port E reset
84pub use AFIORST_W as IOPERST_W;
85///Field `IOPFRST` writer - IO port F reset
86pub use AFIORST_W as IOPFRST_W;
87///Field `IOPGRST` writer - IO port G reset
88pub use AFIORST_W as IOPGRST_W;
89///Field `ADC1RST` writer - ADC 1 interface reset
90pub use AFIORST_W as ADC1RST_W;
91///Field `SPI1RST` writer - SPI 1 reset
92pub use AFIORST_W as SPI1RST_W;
93///Field `USART1RST` writer - USART1 reset
94pub use AFIORST_W as USART1RST_W;
95///Field `TIM9RST` writer - TIM9 timer reset
96pub use AFIORST_W as TIM9RST_W;
97///Field `TIM10RST` writer - TIM10 timer reset
98pub use AFIORST_W as TIM10RST_W;
99///Field `TIM11RST` writer - TIM11 timer reset
100pub use AFIORST_W as TIM11RST_W;
101impl R {
102    ///Bit 0 - Alternate function I/O reset
103    #[inline(always)]
104    pub fn afiorst(&self) -> AFIORST_R {
105        AFIORST_R::new((self.bits & 1) != 0)
106    }
107    ///Bit 2 - IO port A reset
108    #[inline(always)]
109    pub fn ioparst(&self) -> IOPARST_R {
110        IOPARST_R::new(((self.bits >> 2) & 1) != 0)
111    }
112    ///Bit 3 - IO port B reset
113    #[inline(always)]
114    pub fn iopbrst(&self) -> IOPBRST_R {
115        IOPBRST_R::new(((self.bits >> 3) & 1) != 0)
116    }
117    ///Bit 4 - IO port C reset
118    #[inline(always)]
119    pub fn iopcrst(&self) -> IOPCRST_R {
120        IOPCRST_R::new(((self.bits >> 4) & 1) != 0)
121    }
122    ///Bit 5 - IO port D reset
123    #[inline(always)]
124    pub fn iopdrst(&self) -> IOPDRST_R {
125        IOPDRST_R::new(((self.bits >> 5) & 1) != 0)
126    }
127    ///Bit 6 - IO port E reset
128    #[inline(always)]
129    pub fn ioperst(&self) -> IOPERST_R {
130        IOPERST_R::new(((self.bits >> 6) & 1) != 0)
131    }
132    ///Bit 7 - IO port F reset
133    #[inline(always)]
134    pub fn iopfrst(&self) -> IOPFRST_R {
135        IOPFRST_R::new(((self.bits >> 7) & 1) != 0)
136    }
137    ///Bit 8 - IO port G reset
138    #[inline(always)]
139    pub fn iopgrst(&self) -> IOPGRST_R {
140        IOPGRST_R::new(((self.bits >> 8) & 1) != 0)
141    }
142    ///Bit 9 - ADC 1 interface reset
143    #[inline(always)]
144    pub fn adc1rst(&self) -> ADC1RST_R {
145        ADC1RST_R::new(((self.bits >> 9) & 1) != 0)
146    }
147    ///Bit 12 - SPI 1 reset
148    #[inline(always)]
149    pub fn spi1rst(&self) -> SPI1RST_R {
150        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
151    }
152    ///Bit 14 - USART1 reset
153    #[inline(always)]
154    pub fn usart1rst(&self) -> USART1RST_R {
155        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
156    }
157    ///Bit 19 - TIM9 timer reset
158    #[inline(always)]
159    pub fn tim9rst(&self) -> TIM9RST_R {
160        TIM9RST_R::new(((self.bits >> 19) & 1) != 0)
161    }
162    ///Bit 20 - TIM10 timer reset
163    #[inline(always)]
164    pub fn tim10rst(&self) -> TIM10RST_R {
165        TIM10RST_R::new(((self.bits >> 20) & 1) != 0)
166    }
167    ///Bit 21 - TIM11 timer reset
168    #[inline(always)]
169    pub fn tim11rst(&self) -> TIM11RST_R {
170        TIM11RST_R::new(((self.bits >> 21) & 1) != 0)
171    }
172}
173impl core::fmt::Debug for R {
174    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
175        f.debug_struct("APB2RSTR")
176            .field("afiorst", &self.afiorst())
177            .field("ioparst", &self.ioparst())
178            .field("iopbrst", &self.iopbrst())
179            .field("iopcrst", &self.iopcrst())
180            .field("iopdrst", &self.iopdrst())
181            .field("ioperst", &self.ioperst())
182            .field("adc1rst", &self.adc1rst())
183            .field("spi1rst", &self.spi1rst())
184            .field("usart1rst", &self.usart1rst())
185            .field("tim9rst", &self.tim9rst())
186            .field("tim10rst", &self.tim10rst())
187            .field("tim11rst", &self.tim11rst())
188            .field("iopfrst", &self.iopfrst())
189            .field("iopgrst", &self.iopgrst())
190            .finish()
191    }
192}
193impl W {
194    ///Bit 0 - Alternate function I/O reset
195    #[inline(always)]
196    pub fn afiorst(&mut self) -> AFIORST_W<APB2RSTRrs> {
197        AFIORST_W::new(self, 0)
198    }
199    ///Bit 2 - IO port A reset
200    #[inline(always)]
201    pub fn ioparst(&mut self) -> IOPARST_W<APB2RSTRrs> {
202        IOPARST_W::new(self, 2)
203    }
204    ///Bit 3 - IO port B reset
205    #[inline(always)]
206    pub fn iopbrst(&mut self) -> IOPBRST_W<APB2RSTRrs> {
207        IOPBRST_W::new(self, 3)
208    }
209    ///Bit 4 - IO port C reset
210    #[inline(always)]
211    pub fn iopcrst(&mut self) -> IOPCRST_W<APB2RSTRrs> {
212        IOPCRST_W::new(self, 4)
213    }
214    ///Bit 5 - IO port D reset
215    #[inline(always)]
216    pub fn iopdrst(&mut self) -> IOPDRST_W<APB2RSTRrs> {
217        IOPDRST_W::new(self, 5)
218    }
219    ///Bit 6 - IO port E reset
220    #[inline(always)]
221    pub fn ioperst(&mut self) -> IOPERST_W<APB2RSTRrs> {
222        IOPERST_W::new(self, 6)
223    }
224    ///Bit 7 - IO port F reset
225    #[inline(always)]
226    pub fn iopfrst(&mut self) -> IOPFRST_W<APB2RSTRrs> {
227        IOPFRST_W::new(self, 7)
228    }
229    ///Bit 8 - IO port G reset
230    #[inline(always)]
231    pub fn iopgrst(&mut self) -> IOPGRST_W<APB2RSTRrs> {
232        IOPGRST_W::new(self, 8)
233    }
234    ///Bit 9 - ADC 1 interface reset
235    #[inline(always)]
236    pub fn adc1rst(&mut self) -> ADC1RST_W<APB2RSTRrs> {
237        ADC1RST_W::new(self, 9)
238    }
239    ///Bit 12 - SPI 1 reset
240    #[inline(always)]
241    pub fn spi1rst(&mut self) -> SPI1RST_W<APB2RSTRrs> {
242        SPI1RST_W::new(self, 12)
243    }
244    ///Bit 14 - USART1 reset
245    #[inline(always)]
246    pub fn usart1rst(&mut self) -> USART1RST_W<APB2RSTRrs> {
247        USART1RST_W::new(self, 14)
248    }
249    ///Bit 19 - TIM9 timer reset
250    #[inline(always)]
251    pub fn tim9rst(&mut self) -> TIM9RST_W<APB2RSTRrs> {
252        TIM9RST_W::new(self, 19)
253    }
254    ///Bit 20 - TIM10 timer reset
255    #[inline(always)]
256    pub fn tim10rst(&mut self) -> TIM10RST_W<APB2RSTRrs> {
257        TIM10RST_W::new(self, 20)
258    }
259    ///Bit 21 - TIM11 timer reset
260    #[inline(always)]
261    pub fn tim11rst(&mut self) -> TIM11RST_W<APB2RSTRrs> {
262        TIM11RST_W::new(self, 21)
263    }
264}
265/**APB2 peripheral reset register (RCC_APB2RSTR)
266
267You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
268
269See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#RCC:APB2RSTR)*/
270pub struct APB2RSTRrs;
271impl crate::RegisterSpec for APB2RSTRrs {
272    type Ux = u32;
273}
274///`read()` method returns [`apb2rstr::R`](R) reader structure
275impl crate::Readable for APB2RSTRrs {}
276///`write(|w| ..)` method takes [`apb2rstr::W`](W) writer structure
277impl crate::Writable for APB2RSTRrs {
278    type Safety = crate::Unsafe;
279}
280///`reset()` method sets APB2RSTR to value 0
281impl crate::Resettable for APB2RSTRrs {}
stm32f1_staging/stm32f101/rcc/apb2rstr.rs

stm32f1_staging/stm32f101/rcc/
apb2rstr.rs
