stm32f1_staging/stm32f101/rcc/
apb1rstr.rs

1///Register `APB1RSTR` reader
2pub type R = crate::R<APB1RSTRrs>;
3///Register `APB1RSTR` writer
4pub type W = crate::W<APB1RSTRrs>;
5/**Timer 2 reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2RST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<TIM2RST> for bool {
15    #[inline(always)]
16    fn from(variant: TIM2RST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `TIM2RST` reader - Timer 2 reset
21pub type TIM2RST_R = crate::BitReader<TIM2RST>;
22impl TIM2RST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<TIM2RST> {
26        match self.bits {
27            true => Some(TIM2RST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == TIM2RST::Reset
35    }
36}
37///Field `TIM2RST` writer - Timer 2 reset
38pub type TIM2RST_W<'a, REG> = crate::BitWriter<'a, REG, TIM2RST>;
39impl<'a, REG> TIM2RST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(TIM2RST::Reset)
47    }
48}
49///Field `TIM3RST` reader - Timer 3 reset
50pub use TIM2RST_R as TIM3RST_R;
51///Field `TIM4RST` reader - Timer 4 reset
52pub use TIM2RST_R as TIM4RST_R;
53///Field `TIM5RST` reader - Timer 5 reset
54pub use TIM2RST_R as TIM5RST_R;
55///Field `TIM6RST` reader - Timer 6 reset
56pub use TIM2RST_R as TIM6RST_R;
57///Field `TIM7RST` reader - Timer 7 reset
58pub use TIM2RST_R as TIM7RST_R;
59///Field `TIM12RST` reader - Timer 12 reset
60pub use TIM2RST_R as TIM12RST_R;
61///Field `TIM13RST` reader - Timer 13 reset
62pub use TIM2RST_R as TIM13RST_R;
63///Field `TIM14RST` reader - Timer 14 reset
64pub use TIM2RST_R as TIM14RST_R;
65///Field `WWDGRST` reader - Window watchdog reset
66pub use TIM2RST_R as WWDGRST_R;
67///Field `SPI2RST` reader - SPI2 reset
68pub use TIM2RST_R as SPI2RST_R;
69///Field `SPI3RST` reader - SPI3 reset
70pub use TIM2RST_R as SPI3RST_R;
71///Field `USART2RST` reader - USART 2 reset
72pub use TIM2RST_R as USART2RST_R;
73///Field `USART3RST` reader - USART 3 reset
74pub use TIM2RST_R as USART3RST_R;
75///Field `UART4RST` reader - UART 4 reset
76pub use TIM2RST_R as UART4RST_R;
77///Field `UART5RST` reader - UART 5 reset
78pub use TIM2RST_R as UART5RST_R;
79///Field `I2C1RST` reader - I2C1 reset
80pub use TIM2RST_R as I2C1RST_R;
81///Field `I2C2RST` reader - I2C2 reset
82pub use TIM2RST_R as I2C2RST_R;
83///Field `BKPRST` reader - Backup interface reset
84pub use TIM2RST_R as BKPRST_R;
85///Field `PWRRST` reader - Power interface reset
86pub use TIM2RST_R as PWRRST_R;
87///Field `DACRST` reader - DAC interface reset
88pub use TIM2RST_R as DACRST_R;
89///Field `TIM3RST` writer - Timer 3 reset
90pub use TIM2RST_W as TIM3RST_W;
91///Field `TIM4RST` writer - Timer 4 reset
92pub use TIM2RST_W as TIM4RST_W;
93///Field `TIM5RST` writer - Timer 5 reset
94pub use TIM2RST_W as TIM5RST_W;
95///Field `TIM6RST` writer - Timer 6 reset
96pub use TIM2RST_W as TIM6RST_W;
97///Field `TIM7RST` writer - Timer 7 reset
98pub use TIM2RST_W as TIM7RST_W;
99///Field `TIM12RST` writer - Timer 12 reset
100pub use TIM2RST_W as TIM12RST_W;
101///Field `TIM13RST` writer - Timer 13 reset
102pub use TIM2RST_W as TIM13RST_W;
103///Field `TIM14RST` writer - Timer 14 reset
104pub use TIM2RST_W as TIM14RST_W;
105///Field `WWDGRST` writer - Window watchdog reset
106pub use TIM2RST_W as WWDGRST_W;
107///Field `SPI2RST` writer - SPI2 reset
108pub use TIM2RST_W as SPI2RST_W;
109///Field `SPI3RST` writer - SPI3 reset
110pub use TIM2RST_W as SPI3RST_W;
111///Field `USART2RST` writer - USART 2 reset
112pub use TIM2RST_W as USART2RST_W;
113///Field `USART3RST` writer - USART 3 reset
114pub use TIM2RST_W as USART3RST_W;
115///Field `UART4RST` writer - UART 4 reset
116pub use TIM2RST_W as UART4RST_W;
117///Field `UART5RST` writer - UART 5 reset
118pub use TIM2RST_W as UART5RST_W;
119///Field `I2C1RST` writer - I2C1 reset
120pub use TIM2RST_W as I2C1RST_W;
121///Field `I2C2RST` writer - I2C2 reset
122pub use TIM2RST_W as I2C2RST_W;
123///Field `BKPRST` writer - Backup interface reset
124pub use TIM2RST_W as BKPRST_W;
125///Field `PWRRST` writer - Power interface reset
126pub use TIM2RST_W as PWRRST_W;
127///Field `DACRST` writer - DAC interface reset
128pub use TIM2RST_W as DACRST_W;
129impl R {
130    ///Bit 0 - Timer 2 reset
131    #[inline(always)]
132    pub fn tim2rst(&self) -> TIM2RST_R {
133        TIM2RST_R::new((self.bits & 1) != 0)
134    }
135    ///Bit 1 - Timer 3 reset
136    #[inline(always)]
137    pub fn tim3rst(&self) -> TIM3RST_R {
138        TIM3RST_R::new(((self.bits >> 1) & 1) != 0)
139    }
140    ///Bit 2 - Timer 4 reset
141    #[inline(always)]
142    pub fn tim4rst(&self) -> TIM4RST_R {
143        TIM4RST_R::new(((self.bits >> 2) & 1) != 0)
144    }
145    ///Bit 3 - Timer 5 reset
146    #[inline(always)]
147    pub fn tim5rst(&self) -> TIM5RST_R {
148        TIM5RST_R::new(((self.bits >> 3) & 1) != 0)
149    }
150    ///Bit 4 - Timer 6 reset
151    #[inline(always)]
152    pub fn tim6rst(&self) -> TIM6RST_R {
153        TIM6RST_R::new(((self.bits >> 4) & 1) != 0)
154    }
155    ///Bit 5 - Timer 7 reset
156    #[inline(always)]
157    pub fn tim7rst(&self) -> TIM7RST_R {
158        TIM7RST_R::new(((self.bits >> 5) & 1) != 0)
159    }
160    ///Bit 6 - Timer 12 reset
161    #[inline(always)]
162    pub fn tim12rst(&self) -> TIM12RST_R {
163        TIM12RST_R::new(((self.bits >> 6) & 1) != 0)
164    }
165    ///Bit 7 - Timer 13 reset
166    #[inline(always)]
167    pub fn tim13rst(&self) -> TIM13RST_R {
168        TIM13RST_R::new(((self.bits >> 7) & 1) != 0)
169    }
170    ///Bit 8 - Timer 14 reset
171    #[inline(always)]
172    pub fn tim14rst(&self) -> TIM14RST_R {
173        TIM14RST_R::new(((self.bits >> 8) & 1) != 0)
174    }
175    ///Bit 11 - Window watchdog reset
176    #[inline(always)]
177    pub fn wwdgrst(&self) -> WWDGRST_R {
178        WWDGRST_R::new(((self.bits >> 11) & 1) != 0)
179    }
180    ///Bit 14 - SPI2 reset
181    #[inline(always)]
182    pub fn spi2rst(&self) -> SPI2RST_R {
183        SPI2RST_R::new(((self.bits >> 14) & 1) != 0)
184    }
185    ///Bit 15 - SPI3 reset
186    #[inline(always)]
187    pub fn spi3rst(&self) -> SPI3RST_R {
188        SPI3RST_R::new(((self.bits >> 15) & 1) != 0)
189    }
190    ///Bit 17 - USART 2 reset
191    #[inline(always)]
192    pub fn usart2rst(&self) -> USART2RST_R {
193        USART2RST_R::new(((self.bits >> 17) & 1) != 0)
194    }
195    ///Bit 18 - USART 3 reset
196    #[inline(always)]
197    pub fn usart3rst(&self) -> USART3RST_R {
198        USART3RST_R::new(((self.bits >> 18) & 1) != 0)
199    }
200    ///Bit 19 - UART 4 reset
201    #[inline(always)]
202    pub fn uart4rst(&self) -> UART4RST_R {
203        UART4RST_R::new(((self.bits >> 19) & 1) != 0)
204    }
205    ///Bit 20 - UART 5 reset
206    #[inline(always)]
207    pub fn uart5rst(&self) -> UART5RST_R {
208        UART5RST_R::new(((self.bits >> 20) & 1) != 0)
209    }
210    ///Bit 21 - I2C1 reset
211    #[inline(always)]
212    pub fn i2c1rst(&self) -> I2C1RST_R {
213        I2C1RST_R::new(((self.bits >> 21) & 1) != 0)
214    }
215    ///Bit 22 - I2C2 reset
216    #[inline(always)]
217    pub fn i2c2rst(&self) -> I2C2RST_R {
218        I2C2RST_R::new(((self.bits >> 22) & 1) != 0)
219    }
220    ///Bit 27 - Backup interface reset
221    #[inline(always)]
222    pub fn bkprst(&self) -> BKPRST_R {
223        BKPRST_R::new(((self.bits >> 27) & 1) != 0)
224    }
225    ///Bit 28 - Power interface reset
226    #[inline(always)]
227    pub fn pwrrst(&self) -> PWRRST_R {
228        PWRRST_R::new(((self.bits >> 28) & 1) != 0)
229    }
230    ///Bit 29 - DAC interface reset
231    #[inline(always)]
232    pub fn dacrst(&self) -> DACRST_R {
233        DACRST_R::new(((self.bits >> 29) & 1) != 0)
234    }
235}
236impl core::fmt::Debug for R {
237    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
238        f.debug_struct("APB1RSTR")
239            .field("tim2rst", &self.tim2rst())
240            .field("tim3rst", &self.tim3rst())
241            .field("tim4rst", &self.tim4rst())
242            .field("tim5rst", &self.tim5rst())
243            .field("tim6rst", &self.tim6rst())
244            .field("tim7rst", &self.tim7rst())
245            .field("tim12rst", &self.tim12rst())
246            .field("tim13rst", &self.tim13rst())
247            .field("tim14rst", &self.tim14rst())
248            .field("wwdgrst", &self.wwdgrst())
249            .field("spi2rst", &self.spi2rst())
250            .field("spi3rst", &self.spi3rst())
251            .field("usart2rst", &self.usart2rst())
252            .field("usart3rst", &self.usart3rst())
253            .field("uart4rst", &self.uart4rst())
254            .field("uart5rst", &self.uart5rst())
255            .field("i2c1rst", &self.i2c1rst())
256            .field("i2c2rst", &self.i2c2rst())
257            .field("bkprst", &self.bkprst())
258            .field("pwrrst", &self.pwrrst())
259            .field("dacrst", &self.dacrst())
260            .finish()
261    }
262}
263impl W {
264    ///Bit 0 - Timer 2 reset
265    #[inline(always)]
266    pub fn tim2rst(&mut self) -> TIM2RST_W<APB1RSTRrs> {
267        TIM2RST_W::new(self, 0)
268    }
269    ///Bit 1 - Timer 3 reset
270    #[inline(always)]
271    pub fn tim3rst(&mut self) -> TIM3RST_W<APB1RSTRrs> {
272        TIM3RST_W::new(self, 1)
273    }
274    ///Bit 2 - Timer 4 reset
275    #[inline(always)]
276    pub fn tim4rst(&mut self) -> TIM4RST_W<APB1RSTRrs> {
277        TIM4RST_W::new(self, 2)
278    }
279    ///Bit 3 - Timer 5 reset
280    #[inline(always)]
281    pub fn tim5rst(&mut self) -> TIM5RST_W<APB1RSTRrs> {
282        TIM5RST_W::new(self, 3)
283    }
284    ///Bit 4 - Timer 6 reset
285    #[inline(always)]
286    pub fn tim6rst(&mut self) -> TIM6RST_W<APB1RSTRrs> {
287        TIM6RST_W::new(self, 4)
288    }
289    ///Bit 5 - Timer 7 reset
290    #[inline(always)]
291    pub fn tim7rst(&mut self) -> TIM7RST_W<APB1RSTRrs> {
292        TIM7RST_W::new(self, 5)
293    }
294    ///Bit 6 - Timer 12 reset
295    #[inline(always)]
296    pub fn tim12rst(&mut self) -> TIM12RST_W<APB1RSTRrs> {
297        TIM12RST_W::new(self, 6)
298    }
299    ///Bit 7 - Timer 13 reset
300    #[inline(always)]
301    pub fn tim13rst(&mut self) -> TIM13RST_W<APB1RSTRrs> {
302        TIM13RST_W::new(self, 7)
303    }
304    ///Bit 8 - Timer 14 reset
305    #[inline(always)]
306    pub fn tim14rst(&mut self) -> TIM14RST_W<APB1RSTRrs> {
307        TIM14RST_W::new(self, 8)
308    }
309    ///Bit 11 - Window watchdog reset
310    #[inline(always)]
311    pub fn wwdgrst(&mut self) -> WWDGRST_W<APB1RSTRrs> {
312        WWDGRST_W::new(self, 11)
313    }
314    ///Bit 14 - SPI2 reset
315    #[inline(always)]
316    pub fn spi2rst(&mut self) -> SPI2RST_W<APB1RSTRrs> {
317        SPI2RST_W::new(self, 14)
318    }
319    ///Bit 15 - SPI3 reset
320    #[inline(always)]
321    pub fn spi3rst(&mut self) -> SPI3RST_W<APB1RSTRrs> {
322        SPI3RST_W::new(self, 15)
323    }
324    ///Bit 17 - USART 2 reset
325    #[inline(always)]
326    pub fn usart2rst(&mut self) -> USART2RST_W<APB1RSTRrs> {
327        USART2RST_W::new(self, 17)
328    }
329    ///Bit 18 - USART 3 reset
330    #[inline(always)]
331    pub fn usart3rst(&mut self) -> USART3RST_W<APB1RSTRrs> {
332        USART3RST_W::new(self, 18)
333    }
334    ///Bit 19 - UART 4 reset
335    #[inline(always)]
336    pub fn uart4rst(&mut self) -> UART4RST_W<APB1RSTRrs> {
337        UART4RST_W::new(self, 19)
338    }
339    ///Bit 20 - UART 5 reset
340    #[inline(always)]
341    pub fn uart5rst(&mut self) -> UART5RST_W<APB1RSTRrs> {
342        UART5RST_W::new(self, 20)
343    }
344    ///Bit 21 - I2C1 reset
345    #[inline(always)]
346    pub fn i2c1rst(&mut self) -> I2C1RST_W<APB1RSTRrs> {
347        I2C1RST_W::new(self, 21)
348    }
349    ///Bit 22 - I2C2 reset
350    #[inline(always)]
351    pub fn i2c2rst(&mut self) -> I2C2RST_W<APB1RSTRrs> {
352        I2C2RST_W::new(self, 22)
353    }
354    ///Bit 27 - Backup interface reset
355    #[inline(always)]
356    pub fn bkprst(&mut self) -> BKPRST_W<APB1RSTRrs> {
357        BKPRST_W::new(self, 27)
358    }
359    ///Bit 28 - Power interface reset
360    #[inline(always)]
361    pub fn pwrrst(&mut self) -> PWRRST_W<APB1RSTRrs> {
362        PWRRST_W::new(self, 28)
363    }
364    ///Bit 29 - DAC interface reset
365    #[inline(always)]
366    pub fn dacrst(&mut self) -> DACRST_W<APB1RSTRrs> {
367        DACRST_W::new(self, 29)
368    }
369}
370/**APB1 peripheral reset register (RCC_APB1RSTR)
371
372You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
373
374See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#RCC:APB1RSTR)*/
375pub struct APB1RSTRrs;
376impl crate::RegisterSpec for APB1RSTRrs {
377    type Ux = u32;
378}
379///`read()` method returns [`apb1rstr::R`](R) reader structure
380impl crate::Readable for APB1RSTRrs {}
381///`write(|w| ..)` method takes [`apb1rstr::W`](W) writer structure
382impl crate::Writable for APB1RSTRrs {
383    type Safety = crate::Unsafe;
384}
385///`reset()` method sets APB1RSTR to value 0
386impl crate::Resettable for APB1RSTRrs {}
stm32f1_staging/stm32f101/rcc/apb1rstr.rs

stm32f1_staging/stm32f101/rcc/
apb1rstr.rs
