stm32f1_staging/stm32f101/pwr/
csr.rs

1///Register `CSR` reader
2pub type R = crate::R<CSRrs>;
3///Register `CSR` writer
4pub type W = crate::W<CSRrs>;
5///Field `WUF` reader - Wake-Up Flag
6pub type WUF_R = crate::BitReader;
7///Field `SBF` reader - STANDBY Flag
8pub type SBF_R = crate::BitReader;
9///Field `PVDO` reader - PVD Output
10pub type PVDO_R = crate::BitReader;
11///Field `EWUP` reader - Enable WKUP pin
12pub type EWUP_R = crate::BitReader;
13///Field `EWUP` writer - Enable WKUP pin
14pub type EWUP_W<'a, REG> = crate::BitWriter<'a, REG>;
15impl R {
16    ///Bit 0 - Wake-Up Flag
17    #[inline(always)]
18    pub fn wuf(&self) -> WUF_R {
19        WUF_R::new((self.bits & 1) != 0)
20    }
21    ///Bit 1 - STANDBY Flag
22    #[inline(always)]
23    pub fn sbf(&self) -> SBF_R {
24        SBF_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    ///Bit 2 - PVD Output
27    #[inline(always)]
28    pub fn pvdo(&self) -> PVDO_R {
29        PVDO_R::new(((self.bits >> 2) & 1) != 0)
30    }
31    ///Bit 8 - Enable WKUP pin
32    #[inline(always)]
33    pub fn ewup(&self) -> EWUP_R {
34        EWUP_R::new(((self.bits >> 8) & 1) != 0)
35    }
36}
37impl core::fmt::Debug for R {
38    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
39        f.debug_struct("CSR")
40            .field("wuf", &self.wuf())
41            .field("sbf", &self.sbf())
42            .field("pvdo", &self.pvdo())
43            .field("ewup", &self.ewup())
44            .finish()
45    }
46}
47impl W {
48    ///Bit 8 - Enable WKUP pin
49    #[inline(always)]
50    pub fn ewup(&mut self) -> EWUP_W<CSRrs> {
51        EWUP_W::new(self, 8)
52    }
53}
54/**Power control register (PWR_CR)
55
56You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
57
58See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#PWR:CSR)*/
59pub struct CSRrs;
60impl crate::RegisterSpec for CSRrs {
61    type Ux = u32;
62}
63///`read()` method returns [`csr::R`](R) reader structure
64impl crate::Readable for CSRrs {}
65///`write(|w| ..)` method takes [`csr::W`](W) writer structure
66impl crate::Writable for CSRrs {
67    type Safety = crate::Unsafe;
68}
69///`reset()` method sets CSR to value 0
70impl crate::Resettable for CSRrs {}
stm32f1_staging/stm32f101/pwr/csr.rs

stm32f1_staging/stm32f101/pwr/
csr.rs
