stm32f1_staging/stm32f101/i2c1/
oar2.rs

1///Register `OAR2` reader
2pub type R = crate::R<OAR2rs>;
3///Register `OAR2` writer
4pub type W = crate::W<OAR2rs>;
5/**Dual addressing mode enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ENDUAL {
11    ///0: Single addressing mode
12    Single = 0,
13    ///1: Dual addressing mode
14    Dual = 1,
15}
16impl From<ENDUAL> for bool {
17    #[inline(always)]
18    fn from(variant: ENDUAL) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ENDUAL` reader - Dual addressing mode enable
23pub type ENDUAL_R = crate::BitReader<ENDUAL>;
24impl ENDUAL_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ENDUAL {
28        match self.bits {
29            false => ENDUAL::Single,
30            true => ENDUAL::Dual,
31        }
32    }
33    ///Single addressing mode
34    #[inline(always)]
35    pub fn is_single(&self) -> bool {
36        *self == ENDUAL::Single
37    }
38    ///Dual addressing mode
39    #[inline(always)]
40    pub fn is_dual(&self) -> bool {
41        *self == ENDUAL::Dual
42    }
43}
44///Field `ENDUAL` writer - Dual addressing mode enable
45pub type ENDUAL_W<'a, REG> = crate::BitWriter<'a, REG, ENDUAL>;
46impl<'a, REG> ENDUAL_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Single addressing mode
51    #[inline(always)]
52    pub fn single(self) -> &'a mut crate::W<REG> {
53        self.variant(ENDUAL::Single)
54    }
55    ///Dual addressing mode
56    #[inline(always)]
57    pub fn dual(self) -> &'a mut crate::W<REG> {
58        self.variant(ENDUAL::Dual)
59    }
60}
61///Field `ADD2` reader - Interface address
62pub type ADD2_R = crate::FieldReader;
63///Field `ADD2` writer - Interface address
64pub type ADD2_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
65impl R {
66    ///Bit 0 - Dual addressing mode enable
67    #[inline(always)]
68    pub fn endual(&self) -> ENDUAL_R {
69        ENDUAL_R::new((self.bits & 1) != 0)
70    }
71    ///Bits 1:7 - Interface address
72    #[inline(always)]
73    pub fn add2(&self) -> ADD2_R {
74        ADD2_R::new(((self.bits >> 1) & 0x7f) as u8)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("OAR2")
80            .field("add2", &self.add2())
81            .field("endual", &self.endual())
82            .finish()
83    }
84}
85impl W {
86    ///Bit 0 - Dual addressing mode enable
87    #[inline(always)]
88    pub fn endual(&mut self) -> ENDUAL_W<OAR2rs> {
89        ENDUAL_W::new(self, 0)
90    }
91    ///Bits 1:7 - Interface address
92    #[inline(always)]
93    pub fn add2(&mut self) -> ADD2_W<OAR2rs> {
94        ADD2_W::new(self, 1)
95    }
96}
97/**Own address register 2
98
99You can [`read`](crate::Reg::read) this register and get [`oar2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#I2C1:OAR2)*/
102pub struct OAR2rs;
103impl crate::RegisterSpec for OAR2rs {
104    type Ux = u16;
105}
106///`read()` method returns [`oar2::R`](R) reader structure
107impl crate::Readable for OAR2rs {}
108///`write(|w| ..)` method takes [`oar2::W`](W) writer structure
109impl crate::Writable for OAR2rs {
110    type Safety = crate::Unsafe;
111}
112///`reset()` method sets OAR2 to value 0
113impl crate::Resettable for OAR2rs {}
stm32f1_staging/stm32f101/i2c1/oar2.rs

stm32f1_staging/stm32f101/i2c1/
oar2.rs
