stm32f1_staging/stm32f101/gpioa/
lckr.rs

1///Register `LCKR` reader
2pub type R = crate::R<LCKRrs>;
3///Register `LCKR` writer
4pub type W = crate::W<LCKRrs>;
5/**Port A Lock bit %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LOCK {
11    ///0: Port configuration not locked
12    Unlocked = 0,
13    ///1: Port configuration locked
14    Locked = 1,
15}
16impl From<LOCK> for bool {
17    #[inline(always)]
18    fn from(variant: LOCK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LCK(0-15)` reader - Port A Lock bit %s
23pub type LCK_R = crate::BitReader<LOCK>;
24impl LCK_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LOCK {
28        match self.bits {
29            false => LOCK::Unlocked,
30            true => LOCK::Locked,
31        }
32    }
33    ///Port configuration not locked
34    #[inline(always)]
35    pub fn is_unlocked(&self) -> bool {
36        *self == LOCK::Unlocked
37    }
38    ///Port configuration locked
39    #[inline(always)]
40    pub fn is_locked(&self) -> bool {
41        *self == LOCK::Locked
42    }
43}
44///Field `LCK(0-15)` writer - Port A Lock bit %s
45pub type LCK_W<'a, REG> = crate::BitWriter<'a, REG, LOCK>;
46impl<'a, REG> LCK_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Port configuration not locked
51    #[inline(always)]
52    pub fn unlocked(self) -> &'a mut crate::W<REG> {
53        self.variant(LOCK::Unlocked)
54    }
55    ///Port configuration locked
56    #[inline(always)]
57    pub fn locked(self) -> &'a mut crate::W<REG> {
58        self.variant(LOCK::Locked)
59    }
60}
61/**Lock key
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum LOCK_KEY {
67    ///0: Port configuration lock key not active
68    NotActive = 0,
69    ///1: Port configuration lock key active
70    Active = 1,
71}
72impl From<LOCK_KEY> for bool {
73    #[inline(always)]
74    fn from(variant: LOCK_KEY) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `LCKK` reader - Lock key
79pub type LCKK_R = crate::BitReader<LOCK_KEY>;
80impl LCKK_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> LOCK_KEY {
84        match self.bits {
85            false => LOCK_KEY::NotActive,
86            true => LOCK_KEY::Active,
87        }
88    }
89    ///Port configuration lock key not active
90    #[inline(always)]
91    pub fn is_not_active(&self) -> bool {
92        *self == LOCK_KEY::NotActive
93    }
94    ///Port configuration lock key active
95    #[inline(always)]
96    pub fn is_active(&self) -> bool {
97        *self == LOCK_KEY::Active
98    }
99}
100///Field `LCKK` writer - Lock key
101pub type LCKK_W<'a, REG> = crate::BitWriter<'a, REG, LOCK_KEY>;
102impl<'a, REG> LCKK_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Port configuration lock key not active
107    #[inline(always)]
108    pub fn not_active(self) -> &'a mut crate::W<REG> {
109        self.variant(LOCK_KEY::NotActive)
110    }
111    ///Port configuration lock key active
112    #[inline(always)]
113    pub fn active(self) -> &'a mut crate::W<REG> {
114        self.variant(LOCK_KEY::Active)
115    }
116}
117impl R {
118    ///Port A Lock bit (0-15)
119    ///
120    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `LCK0` field.</div>
121    #[inline(always)]
122    pub fn lck(&self, n: u8) -> LCK_R {
123        #[allow(clippy::no_effect)] [(); 16][n as usize];
124        LCK_R::new(((self.bits >> n) & 1) != 0)
125    }
126    ///Iterator for array of:
127    ///Port A Lock bit (0-15)
128    #[inline(always)]
129    pub fn lck_iter(&self) -> impl Iterator<Item = LCK_R> + '_ {
130        (0..16).map(move |n| LCK_R::new(((self.bits >> n) & 1) != 0))
131    }
132    ///Bit 0 - Port A Lock bit 0
133    #[inline(always)]
134    pub fn lck0(&self) -> LCK_R {
135        LCK_R::new((self.bits & 1) != 0)
136    }
137    ///Bit 1 - Port A Lock bit 1
138    #[inline(always)]
139    pub fn lck1(&self) -> LCK_R {
140        LCK_R::new(((self.bits >> 1) & 1) != 0)
141    }
142    ///Bit 2 - Port A Lock bit 2
143    #[inline(always)]
144    pub fn lck2(&self) -> LCK_R {
145        LCK_R::new(((self.bits >> 2) & 1) != 0)
146    }
147    ///Bit 3 - Port A Lock bit 3
148    #[inline(always)]
149    pub fn lck3(&self) -> LCK_R {
150        LCK_R::new(((self.bits >> 3) & 1) != 0)
151    }
152    ///Bit 4 - Port A Lock bit 4
153    #[inline(always)]
154    pub fn lck4(&self) -> LCK_R {
155        LCK_R::new(((self.bits >> 4) & 1) != 0)
156    }
157    ///Bit 5 - Port A Lock bit 5
158    #[inline(always)]
159    pub fn lck5(&self) -> LCK_R {
160        LCK_R::new(((self.bits >> 5) & 1) != 0)
161    }
162    ///Bit 6 - Port A Lock bit 6
163    #[inline(always)]
164    pub fn lck6(&self) -> LCK_R {
165        LCK_R::new(((self.bits >> 6) & 1) != 0)
166    }
167    ///Bit 7 - Port A Lock bit 7
168    #[inline(always)]
169    pub fn lck7(&self) -> LCK_R {
170        LCK_R::new(((self.bits >> 7) & 1) != 0)
171    }
172    ///Bit 8 - Port A Lock bit 8
173    #[inline(always)]
174    pub fn lck8(&self) -> LCK_R {
175        LCK_R::new(((self.bits >> 8) & 1) != 0)
176    }
177    ///Bit 9 - Port A Lock bit 9
178    #[inline(always)]
179    pub fn lck9(&self) -> LCK_R {
180        LCK_R::new(((self.bits >> 9) & 1) != 0)
181    }
182    ///Bit 10 - Port A Lock bit 10
183    #[inline(always)]
184    pub fn lck10(&self) -> LCK_R {
185        LCK_R::new(((self.bits >> 10) & 1) != 0)
186    }
187    ///Bit 11 - Port A Lock bit 11
188    #[inline(always)]
189    pub fn lck11(&self) -> LCK_R {
190        LCK_R::new(((self.bits >> 11) & 1) != 0)
191    }
192    ///Bit 12 - Port A Lock bit 12
193    #[inline(always)]
194    pub fn lck12(&self) -> LCK_R {
195        LCK_R::new(((self.bits >> 12) & 1) != 0)
196    }
197    ///Bit 13 - Port A Lock bit 13
198    #[inline(always)]
199    pub fn lck13(&self) -> LCK_R {
200        LCK_R::new(((self.bits >> 13) & 1) != 0)
201    }
202    ///Bit 14 - Port A Lock bit 14
203    #[inline(always)]
204    pub fn lck14(&self) -> LCK_R {
205        LCK_R::new(((self.bits >> 14) & 1) != 0)
206    }
207    ///Bit 15 - Port A Lock bit 15
208    #[inline(always)]
209    pub fn lck15(&self) -> LCK_R {
210        LCK_R::new(((self.bits >> 15) & 1) != 0)
211    }
212    ///Bit 16 - Lock key
213    #[inline(always)]
214    pub fn lckk(&self) -> LCKK_R {
215        LCKK_R::new(((self.bits >> 16) & 1) != 0)
216    }
217}
218impl core::fmt::Debug for R {
219    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
220        f.debug_struct("LCKR")
221            .field("lck0", &self.lck0())
222            .field("lck1", &self.lck1())
223            .field("lck2", &self.lck2())
224            .field("lck3", &self.lck3())
225            .field("lck4", &self.lck4())
226            .field("lck5", &self.lck5())
227            .field("lck6", &self.lck6())
228            .field("lck7", &self.lck7())
229            .field("lck8", &self.lck8())
230            .field("lck9", &self.lck9())
231            .field("lck10", &self.lck10())
232            .field("lck11", &self.lck11())
233            .field("lck12", &self.lck12())
234            .field("lck13", &self.lck13())
235            .field("lck14", &self.lck14())
236            .field("lck15", &self.lck15())
237            .field("lckk", &self.lckk())
238            .finish()
239    }
240}
241impl W {
242    ///Port A Lock bit (0-15)
243    ///
244    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `LCK0` field.</div>
245    #[inline(always)]
246    pub fn lck(&mut self, n: u8) -> LCK_W<LCKRrs> {
247        #[allow(clippy::no_effect)] [(); 16][n as usize];
248        LCK_W::new(self, n)
249    }
250    ///Bit 0 - Port A Lock bit 0
251    #[inline(always)]
252    pub fn lck0(&mut self) -> LCK_W<LCKRrs> {
253        LCK_W::new(self, 0)
254    }
255    ///Bit 1 - Port A Lock bit 1
256    #[inline(always)]
257    pub fn lck1(&mut self) -> LCK_W<LCKRrs> {
258        LCK_W::new(self, 1)
259    }
260    ///Bit 2 - Port A Lock bit 2
261    #[inline(always)]
262    pub fn lck2(&mut self) -> LCK_W<LCKRrs> {
263        LCK_W::new(self, 2)
264    }
265    ///Bit 3 - Port A Lock bit 3
266    #[inline(always)]
267    pub fn lck3(&mut self) -> LCK_W<LCKRrs> {
268        LCK_W::new(self, 3)
269    }
270    ///Bit 4 - Port A Lock bit 4
271    #[inline(always)]
272    pub fn lck4(&mut self) -> LCK_W<LCKRrs> {
273        LCK_W::new(self, 4)
274    }
275    ///Bit 5 - Port A Lock bit 5
276    #[inline(always)]
277    pub fn lck5(&mut self) -> LCK_W<LCKRrs> {
278        LCK_W::new(self, 5)
279    }
280    ///Bit 6 - Port A Lock bit 6
281    #[inline(always)]
282    pub fn lck6(&mut self) -> LCK_W<LCKRrs> {
283        LCK_W::new(self, 6)
284    }
285    ///Bit 7 - Port A Lock bit 7
286    #[inline(always)]
287    pub fn lck7(&mut self) -> LCK_W<LCKRrs> {
288        LCK_W::new(self, 7)
289    }
290    ///Bit 8 - Port A Lock bit 8
291    #[inline(always)]
292    pub fn lck8(&mut self) -> LCK_W<LCKRrs> {
293        LCK_W::new(self, 8)
294    }
295    ///Bit 9 - Port A Lock bit 9
296    #[inline(always)]
297    pub fn lck9(&mut self) -> LCK_W<LCKRrs> {
298        LCK_W::new(self, 9)
299    }
300    ///Bit 10 - Port A Lock bit 10
301    #[inline(always)]
302    pub fn lck10(&mut self) -> LCK_W<LCKRrs> {
303        LCK_W::new(self, 10)
304    }
305    ///Bit 11 - Port A Lock bit 11
306    #[inline(always)]
307    pub fn lck11(&mut self) -> LCK_W<LCKRrs> {
308        LCK_W::new(self, 11)
309    }
310    ///Bit 12 - Port A Lock bit 12
311    #[inline(always)]
312    pub fn lck12(&mut self) -> LCK_W<LCKRrs> {
313        LCK_W::new(self, 12)
314    }
315    ///Bit 13 - Port A Lock bit 13
316    #[inline(always)]
317    pub fn lck13(&mut self) -> LCK_W<LCKRrs> {
318        LCK_W::new(self, 13)
319    }
320    ///Bit 14 - Port A Lock bit 14
321    #[inline(always)]
322    pub fn lck14(&mut self) -> LCK_W<LCKRrs> {
323        LCK_W::new(self, 14)
324    }
325    ///Bit 15 - Port A Lock bit 15
326    #[inline(always)]
327    pub fn lck15(&mut self) -> LCK_W<LCKRrs> {
328        LCK_W::new(self, 15)
329    }
330    ///Bit 16 - Lock key
331    #[inline(always)]
332    pub fn lckk(&mut self) -> LCKK_W<LCKRrs> {
333        LCKK_W::new(self, 16)
334    }
335}
336/**Port configuration lock register
337
338You can [`read`](crate::Reg::read) this register and get [`lckr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lckr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
339
340See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#GPIOA:LCKR)*/
341pub struct LCKRrs;
342impl crate::RegisterSpec for LCKRrs {
343    type Ux = u32;
344}
345///`read()` method returns [`lckr::R`](R) reader structure
346impl crate::Readable for LCKRrs {}
347///`write(|w| ..)` method takes [`lckr::W`](W) writer structure
348impl crate::Writable for LCKRrs {
349    type Safety = crate::Unsafe;
350}
351///`reset()` method sets LCKR to value 0
352impl crate::Resettable for LCKRrs {}
stm32f1_staging/stm32f101/gpioa/lckr.rs

stm32f1_staging/stm32f101/gpioa/
lckr.rs
