stm32f1_staging/stm32f101/fsmc/
pcr4.rs

1///Register `PCR4` reader
2pub type R = crate::R<PCR4rs>;
3///Register `PCR4` writer
4pub type W = crate::W<PCR4rs>;
5///Field `PWAITEN` reader - PWAITEN
6pub type PWAITEN_R = crate::BitReader;
7///Field `PWAITEN` writer - PWAITEN
8pub type PWAITEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `PBKEN` reader - PBKEN
10pub type PBKEN_R = crate::BitReader;
11///Field `PBKEN` writer - PBKEN
12pub type PBKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `PTYP` reader - PTYP
14pub type PTYP_R = crate::BitReader;
15///Field `PTYP` writer - PTYP
16pub type PTYP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `PWID` reader - PWID
18pub type PWID_R = crate::FieldReader;
19///Field `PWID` writer - PWID
20pub type PWID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21///Field `ECCEN` reader - ECCEN
22pub type ECCEN_R = crate::BitReader;
23///Field `ECCEN` writer - ECCEN
24pub type ECCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `TCLR` reader - TCLR
26pub type TCLR_R = crate::FieldReader;
27///Field `TCLR` writer - TCLR
28pub type TCLR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29///Field `TAR` reader - TAR
30pub type TAR_R = crate::FieldReader;
31///Field `TAR` writer - TAR
32pub type TAR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33///Field `ECCPS` reader - ECCPS
34pub type ECCPS_R = crate::FieldReader;
35///Field `ECCPS` writer - ECCPS
36pub type ECCPS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37impl R {
38    ///Bit 1 - PWAITEN
39    #[inline(always)]
40    pub fn pwaiten(&self) -> PWAITEN_R {
41        PWAITEN_R::new(((self.bits >> 1) & 1) != 0)
42    }
43    ///Bit 2 - PBKEN
44    #[inline(always)]
45    pub fn pbken(&self) -> PBKEN_R {
46        PBKEN_R::new(((self.bits >> 2) & 1) != 0)
47    }
48    ///Bit 3 - PTYP
49    #[inline(always)]
50    pub fn ptyp(&self) -> PTYP_R {
51        PTYP_R::new(((self.bits >> 3) & 1) != 0)
52    }
53    ///Bits 4:5 - PWID
54    #[inline(always)]
55    pub fn pwid(&self) -> PWID_R {
56        PWID_R::new(((self.bits >> 4) & 3) as u8)
57    }
58    ///Bit 6 - ECCEN
59    #[inline(always)]
60    pub fn eccen(&self) -> ECCEN_R {
61        ECCEN_R::new(((self.bits >> 6) & 1) != 0)
62    }
63    ///Bits 9:12 - TCLR
64    #[inline(always)]
65    pub fn tclr(&self) -> TCLR_R {
66        TCLR_R::new(((self.bits >> 9) & 0x0f) as u8)
67    }
68    ///Bits 13:16 - TAR
69    #[inline(always)]
70    pub fn tar(&self) -> TAR_R {
71        TAR_R::new(((self.bits >> 13) & 0x0f) as u8)
72    }
73    ///Bits 17:19 - ECCPS
74    #[inline(always)]
75    pub fn eccps(&self) -> ECCPS_R {
76        ECCPS_R::new(((self.bits >> 17) & 7) as u8)
77    }
78}
79impl core::fmt::Debug for R {
80    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
81        f.debug_struct("PCR4")
82            .field("eccps", &self.eccps())
83            .field("tar", &self.tar())
84            .field("tclr", &self.tclr())
85            .field("eccen", &self.eccen())
86            .field("pwid", &self.pwid())
87            .field("ptyp", &self.ptyp())
88            .field("pbken", &self.pbken())
89            .field("pwaiten", &self.pwaiten())
90            .finish()
91    }
92}
93impl W {
94    ///Bit 1 - PWAITEN
95    #[inline(always)]
96    pub fn pwaiten(&mut self) -> PWAITEN_W<PCR4rs> {
97        PWAITEN_W::new(self, 1)
98    }
99    ///Bit 2 - PBKEN
100    #[inline(always)]
101    pub fn pbken(&mut self) -> PBKEN_W<PCR4rs> {
102        PBKEN_W::new(self, 2)
103    }
104    ///Bit 3 - PTYP
105    #[inline(always)]
106    pub fn ptyp(&mut self) -> PTYP_W<PCR4rs> {
107        PTYP_W::new(self, 3)
108    }
109    ///Bits 4:5 - PWID
110    #[inline(always)]
111    pub fn pwid(&mut self) -> PWID_W<PCR4rs> {
112        PWID_W::new(self, 4)
113    }
114    ///Bit 6 - ECCEN
115    #[inline(always)]
116    pub fn eccen(&mut self) -> ECCEN_W<PCR4rs> {
117        ECCEN_W::new(self, 6)
118    }
119    ///Bits 9:12 - TCLR
120    #[inline(always)]
121    pub fn tclr(&mut self) -> TCLR_W<PCR4rs> {
122        TCLR_W::new(self, 9)
123    }
124    ///Bits 13:16 - TAR
125    #[inline(always)]
126    pub fn tar(&mut self) -> TAR_W<PCR4rs> {
127        TAR_W::new(self, 13)
128    }
129    ///Bits 17:19 - ECCPS
130    #[inline(always)]
131    pub fn eccps(&mut self) -> ECCPS_W<PCR4rs> {
132        ECCPS_W::new(self, 17)
133    }
134}
135/**PC Card/NAND Flash control register 4
136
137You can [`read`](crate::Reg::read) this register and get [`pcr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PCR4)*/
140pub struct PCR4rs;
141impl crate::RegisterSpec for PCR4rs {
142    type Ux = u32;
143}
144///`read()` method returns [`pcr4::R`](R) reader structure
145impl crate::Readable for PCR4rs {}
146///`write(|w| ..)` method takes [`pcr4::W`](W) writer structure
147impl crate::Writable for PCR4rs {
148    type Safety = crate::Unsafe;
149}
150///`reset()` method sets PCR4 to value 0x18
151impl crate::Resettable for PCR4rs {
152    const RESET_VALUE: u32 = 0x18;
153}
stm32f1_staging/stm32f101/fsmc/pcr4.rs

stm32f1_staging/stm32f101/fsmc/
pcr4.rs
