stm32f1_staging/stm32f101/afio/
mapr2.rs

1///Register `MAPR2` reader
2pub type R = crate::R<MAPR2rs>;
3///Register `MAPR2` writer
4pub type W = crate::W<MAPR2rs>;
5///Field `TIM9_REMAP` reader - TIM9 remapping
6pub type TIM9_REMAP_R = crate::BitReader;
7///Field `TIM9_REMAP` writer - TIM9 remapping
8pub type TIM9_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `TIM10_REMAP` reader - TIM10 remapping
10pub type TIM10_REMAP_R = crate::BitReader;
11///Field `TIM10_REMAP` writer - TIM10 remapping
12pub type TIM10_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TIM11_REMAP` reader - TIM11 remapping
14pub type TIM11_REMAP_R = crate::BitReader;
15///Field `TIM11_REMAP` writer - TIM11 remapping
16pub type TIM11_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `TIM13_REMAP` reader - TIM13 remapping
18pub type TIM13_REMAP_R = crate::BitReader;
19///Field `TIM13_REMAP` writer - TIM13 remapping
20pub type TIM13_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TIM14_REMAP` reader - TIM14 remapping
22pub type TIM14_REMAP_R = crate::BitReader;
23///Field `TIM14_REMAP` writer - TIM14 remapping
24pub type TIM14_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `FSMC_NADV` reader - NADV connect/disconnect
26pub type FSMC_NADV_R = crate::BitReader;
27///Field `FSMC_NADV` writer - NADV connect/disconnect
28pub type FSMC_NADV_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    ///Bit 5 - TIM9 remapping
31    #[inline(always)]
32    pub fn tim9_remap(&self) -> TIM9_REMAP_R {
33        TIM9_REMAP_R::new(((self.bits >> 5) & 1) != 0)
34    }
35    ///Bit 6 - TIM10 remapping
36    #[inline(always)]
37    pub fn tim10_remap(&self) -> TIM10_REMAP_R {
38        TIM10_REMAP_R::new(((self.bits >> 6) & 1) != 0)
39    }
40    ///Bit 7 - TIM11 remapping
41    #[inline(always)]
42    pub fn tim11_remap(&self) -> TIM11_REMAP_R {
43        TIM11_REMAP_R::new(((self.bits >> 7) & 1) != 0)
44    }
45    ///Bit 8 - TIM13 remapping
46    #[inline(always)]
47    pub fn tim13_remap(&self) -> TIM13_REMAP_R {
48        TIM13_REMAP_R::new(((self.bits >> 8) & 1) != 0)
49    }
50    ///Bit 9 - TIM14 remapping
51    #[inline(always)]
52    pub fn tim14_remap(&self) -> TIM14_REMAP_R {
53        TIM14_REMAP_R::new(((self.bits >> 9) & 1) != 0)
54    }
55    ///Bit 10 - NADV connect/disconnect
56    #[inline(always)]
57    pub fn fsmc_nadv(&self) -> FSMC_NADV_R {
58        FSMC_NADV_R::new(((self.bits >> 10) & 1) != 0)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("MAPR2")
64            .field("tim9_remap", &self.tim9_remap())
65            .field("tim10_remap", &self.tim10_remap())
66            .field("tim11_remap", &self.tim11_remap())
67            .field("tim13_remap", &self.tim13_remap())
68            .field("tim14_remap", &self.tim14_remap())
69            .field("fsmc_nadv", &self.fsmc_nadv())
70            .finish()
71    }
72}
73impl W {
74    ///Bit 5 - TIM9 remapping
75    #[inline(always)]
76    pub fn tim9_remap(&mut self) -> TIM9_REMAP_W<MAPR2rs> {
77        TIM9_REMAP_W::new(self, 5)
78    }
79    ///Bit 6 - TIM10 remapping
80    #[inline(always)]
81    pub fn tim10_remap(&mut self) -> TIM10_REMAP_W<MAPR2rs> {
82        TIM10_REMAP_W::new(self, 6)
83    }
84    ///Bit 7 - TIM11 remapping
85    #[inline(always)]
86    pub fn tim11_remap(&mut self) -> TIM11_REMAP_W<MAPR2rs> {
87        TIM11_REMAP_W::new(self, 7)
88    }
89    ///Bit 8 - TIM13 remapping
90    #[inline(always)]
91    pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<MAPR2rs> {
92        TIM13_REMAP_W::new(self, 8)
93    }
94    ///Bit 9 - TIM14 remapping
95    #[inline(always)]
96    pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<MAPR2rs> {
97        TIM14_REMAP_W::new(self, 9)
98    }
99    ///Bit 10 - NADV connect/disconnect
100    #[inline(always)]
101    pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<MAPR2rs> {
102        FSMC_NADV_W::new(self, 10)
103    }
104}
105/**AF remap and debug I/O configuration register
106
107You can [`read`](crate::Reg::read) this register and get [`mapr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mapr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#AFIO:MAPR2)*/
110pub struct MAPR2rs;
111impl crate::RegisterSpec for MAPR2rs {
112    type Ux = u32;
113}
114///`read()` method returns [`mapr2::R`](R) reader structure
115impl crate::Readable for MAPR2rs {}
116///`write(|w| ..)` method takes [`mapr2::W`](W) writer structure
117impl crate::Writable for MAPR2rs {
118    type Safety = crate::Unsafe;
119}
120///`reset()` method sets MAPR2 to value 0
121impl crate::Resettable for MAPR2rs {}
stm32f1_staging/stm32f101/afio/mapr2.rs

stm32f1_staging/stm32f101/afio/
mapr2.rs
