stm32f1_staging/stm32f101/afio/
mapr.rs

1///Register `MAPR` reader
2pub type R = crate::R<MAPRrs>;
3///Register `MAPR` writer
4pub type W = crate::W<MAPRrs>;
5///Field `SPI1_REMAP` reader - SPI1 remapping
6pub type SPI1_REMAP_R = crate::BitReader;
7///Field `SPI1_REMAP` writer - SPI1 remapping
8pub type SPI1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `I2C1_REMAP` reader - I2C1 remapping
10pub type I2C1_REMAP_R = crate::BitReader;
11///Field `I2C1_REMAP` writer - I2C1 remapping
12pub type I2C1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `USART1_REMAP` reader - USART1 remapping
14pub type USART1_REMAP_R = crate::BitReader;
15///Field `USART1_REMAP` writer - USART1 remapping
16pub type USART1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `USART2_REMAP` reader - USART2 remapping
18pub type USART2_REMAP_R = crate::BitReader;
19///Field `USART2_REMAP` writer - USART2 remapping
20pub type USART2_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `USART3_REMAP` reader - USART3 remapping
22pub type USART3_REMAP_R = crate::FieldReader;
23///Field `USART3_REMAP` writer - USART3 remapping
24pub type USART3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `TIM1_REMAP` reader - TIM1 remapping
26pub type TIM1_REMAP_R = crate::FieldReader;
27///Field `TIM1_REMAP` writer - TIM1 remapping
28pub type TIM1_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `TIM2_REMAP` reader - TIM2 remapping
30pub type TIM2_REMAP_R = crate::FieldReader;
31///Field `TIM2_REMAP` writer - TIM2 remapping
32pub type TIM2_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33///Field `TIM3_REMAP` reader - TIM3 remapping
34pub type TIM3_REMAP_R = crate::FieldReader;
35///Field `TIM3_REMAP` writer - TIM3 remapping
36pub type TIM3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37///Field `TIM4_REMAP` reader - TIM4 remapping
38pub type TIM4_REMAP_R = crate::BitReader;
39///Field `TIM4_REMAP` writer - TIM4 remapping
40pub type TIM4_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `CAN_REMAP` reader - CAN1 remapping
42pub type CAN_REMAP_R = crate::FieldReader;
43///Field `CAN_REMAP` writer - CAN1 remapping
44pub type CAN_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45///Field `PD01_REMAP` reader - Port D0/Port D1 mapping on OSCIN/OSCOUT
46pub type PD01_REMAP_R = crate::BitReader;
47///Field `PD01_REMAP` writer - Port D0/Port D1 mapping on OSCIN/OSCOUT
48pub type PD01_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `TIM5CH4_IREMAP` reader - Set and cleared by software
50pub type TIM5CH4_IREMAP_R = crate::BitReader;
51///Field `TIM5CH4_IREMAP` writer - Set and cleared by software
52pub type TIM5CH4_IREMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `ADC1_ETRGINJ_REMAP` reader - ADC 1 External trigger injected conversion remapping
54pub type ADC1_ETRGINJ_REMAP_R = crate::BitReader;
55///Field `ADC1_ETRGINJ_REMAP` writer - ADC 1 External trigger injected conversion remapping
56pub type ADC1_ETRGINJ_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `ADC1_ETRGREG_REMAP` reader - ADC 1 external trigger regular conversion remapping
58pub type ADC1_ETRGREG_REMAP_R = crate::BitReader;
59///Field `ADC1_ETRGREG_REMAP` writer - ADC 1 external trigger regular conversion remapping
60pub type ADC1_ETRGREG_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `ADC2_ETRGINJ_REMAP` reader - ADC 2 external trigger injected conversion remapping
62pub type ADC2_ETRGINJ_REMAP_R = crate::BitReader;
63///Field `ADC2_ETRGINJ_REMAP` writer - ADC 2 external trigger injected conversion remapping
64pub type ADC2_ETRGINJ_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `ADC2_ETRGREG_REMAP` reader - ADC 2 external trigger regular conversion remapping
66pub type ADC2_ETRGREG_REMAP_R = crate::BitReader;
67///Field `ADC2_ETRGREG_REMAP` writer - ADC 2 external trigger regular conversion remapping
68pub type ADC2_ETRGREG_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `SWJ_CFG` writer - Serial wire JTAG configuration
70pub type SWJ_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
71impl R {
72    ///Bit 0 - SPI1 remapping
73    #[inline(always)]
74    pub fn spi1_remap(&self) -> SPI1_REMAP_R {
75        SPI1_REMAP_R::new((self.bits & 1) != 0)
76    }
77    ///Bit 1 - I2C1 remapping
78    #[inline(always)]
79    pub fn i2c1_remap(&self) -> I2C1_REMAP_R {
80        I2C1_REMAP_R::new(((self.bits >> 1) & 1) != 0)
81    }
82    ///Bit 2 - USART1 remapping
83    #[inline(always)]
84    pub fn usart1_remap(&self) -> USART1_REMAP_R {
85        USART1_REMAP_R::new(((self.bits >> 2) & 1) != 0)
86    }
87    ///Bit 3 - USART2 remapping
88    #[inline(always)]
89    pub fn usart2_remap(&self) -> USART2_REMAP_R {
90        USART2_REMAP_R::new(((self.bits >> 3) & 1) != 0)
91    }
92    ///Bits 4:5 - USART3 remapping
93    #[inline(always)]
94    pub fn usart3_remap(&self) -> USART3_REMAP_R {
95        USART3_REMAP_R::new(((self.bits >> 4) & 3) as u8)
96    }
97    ///Bits 6:7 - TIM1 remapping
98    #[inline(always)]
99    pub fn tim1_remap(&self) -> TIM1_REMAP_R {
100        TIM1_REMAP_R::new(((self.bits >> 6) & 3) as u8)
101    }
102    ///Bits 8:9 - TIM2 remapping
103    #[inline(always)]
104    pub fn tim2_remap(&self) -> TIM2_REMAP_R {
105        TIM2_REMAP_R::new(((self.bits >> 8) & 3) as u8)
106    }
107    ///Bits 10:11 - TIM3 remapping
108    #[inline(always)]
109    pub fn tim3_remap(&self) -> TIM3_REMAP_R {
110        TIM3_REMAP_R::new(((self.bits >> 10) & 3) as u8)
111    }
112    ///Bit 12 - TIM4 remapping
113    #[inline(always)]
114    pub fn tim4_remap(&self) -> TIM4_REMAP_R {
115        TIM4_REMAP_R::new(((self.bits >> 12) & 1) != 0)
116    }
117    ///Bits 13:14 - CAN1 remapping
118    #[inline(always)]
119    pub fn can_remap(&self) -> CAN_REMAP_R {
120        CAN_REMAP_R::new(((self.bits >> 13) & 3) as u8)
121    }
122    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
123    #[inline(always)]
124    pub fn pd01_remap(&self) -> PD01_REMAP_R {
125        PD01_REMAP_R::new(((self.bits >> 15) & 1) != 0)
126    }
127    ///Bit 16 - Set and cleared by software
128    #[inline(always)]
129    pub fn tim5ch4_iremap(&self) -> TIM5CH4_IREMAP_R {
130        TIM5CH4_IREMAP_R::new(((self.bits >> 16) & 1) != 0)
131    }
132    ///Bit 17 - ADC 1 External trigger injected conversion remapping
133    #[inline(always)]
134    pub fn adc1_etrginj_remap(&self) -> ADC1_ETRGINJ_REMAP_R {
135        ADC1_ETRGINJ_REMAP_R::new(((self.bits >> 17) & 1) != 0)
136    }
137    ///Bit 18 - ADC 1 external trigger regular conversion remapping
138    #[inline(always)]
139    pub fn adc1_etrgreg_remap(&self) -> ADC1_ETRGREG_REMAP_R {
140        ADC1_ETRGREG_REMAP_R::new(((self.bits >> 18) & 1) != 0)
141    }
142    ///Bit 19 - ADC 2 external trigger injected conversion remapping
143    #[inline(always)]
144    pub fn adc2_etrginj_remap(&self) -> ADC2_ETRGINJ_REMAP_R {
145        ADC2_ETRGINJ_REMAP_R::new(((self.bits >> 19) & 1) != 0)
146    }
147    ///Bit 20 - ADC 2 external trigger regular conversion remapping
148    #[inline(always)]
149    pub fn adc2_etrgreg_remap(&self) -> ADC2_ETRGREG_REMAP_R {
150        ADC2_ETRGREG_REMAP_R::new(((self.bits >> 20) & 1) != 0)
151    }
152}
153impl core::fmt::Debug for R {
154    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
155        f.debug_struct("MAPR")
156            .field("spi1_remap", &self.spi1_remap())
157            .field("i2c1_remap", &self.i2c1_remap())
158            .field("usart1_remap", &self.usart1_remap())
159            .field("usart2_remap", &self.usart2_remap())
160            .field("usart3_remap", &self.usart3_remap())
161            .field("tim1_remap", &self.tim1_remap())
162            .field("tim2_remap", &self.tim2_remap())
163            .field("tim3_remap", &self.tim3_remap())
164            .field("tim4_remap", &self.tim4_remap())
165            .field("can_remap", &self.can_remap())
166            .field("pd01_remap", &self.pd01_remap())
167            .field("tim5ch4_iremap", &self.tim5ch4_iremap())
168            .field("adc1_etrginj_remap", &self.adc1_etrginj_remap())
169            .field("adc1_etrgreg_remap", &self.adc1_etrgreg_remap())
170            .field("adc2_etrginj_remap", &self.adc2_etrginj_remap())
171            .field("adc2_etrgreg_remap", &self.adc2_etrgreg_remap())
172            .finish()
173    }
174}
175impl W {
176    ///Bit 0 - SPI1 remapping
177    #[inline(always)]
178    pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<MAPRrs> {
179        SPI1_REMAP_W::new(self, 0)
180    }
181    ///Bit 1 - I2C1 remapping
182    #[inline(always)]
183    pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<MAPRrs> {
184        I2C1_REMAP_W::new(self, 1)
185    }
186    ///Bit 2 - USART1 remapping
187    #[inline(always)]
188    pub fn usart1_remap(&mut self) -> USART1_REMAP_W<MAPRrs> {
189        USART1_REMAP_W::new(self, 2)
190    }
191    ///Bit 3 - USART2 remapping
192    #[inline(always)]
193    pub fn usart2_remap(&mut self) -> USART2_REMAP_W<MAPRrs> {
194        USART2_REMAP_W::new(self, 3)
195    }
196    ///Bits 4:5 - USART3 remapping
197    #[inline(always)]
198    pub fn usart3_remap(&mut self) -> USART3_REMAP_W<MAPRrs> {
199        USART3_REMAP_W::new(self, 4)
200    }
201    ///Bits 6:7 - TIM1 remapping
202    #[inline(always)]
203    pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<MAPRrs> {
204        TIM1_REMAP_W::new(self, 6)
205    }
206    ///Bits 8:9 - TIM2 remapping
207    #[inline(always)]
208    pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<MAPRrs> {
209        TIM2_REMAP_W::new(self, 8)
210    }
211    ///Bits 10:11 - TIM3 remapping
212    #[inline(always)]
213    pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<MAPRrs> {
214        TIM3_REMAP_W::new(self, 10)
215    }
216    ///Bit 12 - TIM4 remapping
217    #[inline(always)]
218    pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<MAPRrs> {
219        TIM4_REMAP_W::new(self, 12)
220    }
221    ///Bits 13:14 - CAN1 remapping
222    #[inline(always)]
223    pub fn can_remap(&mut self) -> CAN_REMAP_W<MAPRrs> {
224        CAN_REMAP_W::new(self, 13)
225    }
226    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
227    #[inline(always)]
228    pub fn pd01_remap(&mut self) -> PD01_REMAP_W<MAPRrs> {
229        PD01_REMAP_W::new(self, 15)
230    }
231    ///Bit 16 - Set and cleared by software
232    #[inline(always)]
233    pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<MAPRrs> {
234        TIM5CH4_IREMAP_W::new(self, 16)
235    }
236    ///Bit 17 - ADC 1 External trigger injected conversion remapping
237    #[inline(always)]
238    pub fn adc1_etrginj_remap(&mut self) -> ADC1_ETRGINJ_REMAP_W<MAPRrs> {
239        ADC1_ETRGINJ_REMAP_W::new(self, 17)
240    }
241    ///Bit 18 - ADC 1 external trigger regular conversion remapping
242    #[inline(always)]
243    pub fn adc1_etrgreg_remap(&mut self) -> ADC1_ETRGREG_REMAP_W<MAPRrs> {
244        ADC1_ETRGREG_REMAP_W::new(self, 18)
245    }
246    ///Bit 19 - ADC 2 external trigger injected conversion remapping
247    #[inline(always)]
248    pub fn adc2_etrginj_remap(&mut self) -> ADC2_ETRGINJ_REMAP_W<MAPRrs> {
249        ADC2_ETRGINJ_REMAP_W::new(self, 19)
250    }
251    ///Bit 20 - ADC 2 external trigger regular conversion remapping
252    #[inline(always)]
253    pub fn adc2_etrgreg_remap(&mut self) -> ADC2_ETRGREG_REMAP_W<MAPRrs> {
254        ADC2_ETRGREG_REMAP_W::new(self, 20)
255    }
256    ///Bits 24:26 - Serial wire JTAG configuration
257    #[inline(always)]
258    pub fn swj_cfg(&mut self) -> SWJ_CFG_W<MAPRrs> {
259        SWJ_CFG_W::new(self, 24)
260    }
261}
262/**AF remap and debug I/O configuration register (AFIO_MAPR)
263
264You can [`read`](crate::Reg::read) this register and get [`mapr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mapr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
265
266See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#AFIO:MAPR)*/
267pub struct MAPRrs;
268impl crate::RegisterSpec for MAPRrs {
269    type Ux = u32;
270}
271///`read()` method returns [`mapr::R`](R) reader structure
272impl crate::Readable for MAPRrs {}
273///`write(|w| ..)` method takes [`mapr::W`](W) writer structure
274impl crate::Writable for MAPRrs {
275    type Safety = crate::Unsafe;
276}
277///`reset()` method sets MAPR to value 0
278impl crate::Resettable for MAPRrs {}
stm32f1_staging/stm32f101/afio/mapr.rs

stm32f1_staging/stm32f101/afio/
mapr.rs
