stm32f1_staging/stm32f101/afio/
exticr2.rs

1///Register `EXTICR2` reader
2pub type R = crate::R<EXTICR2rs>;
3///Register `EXTICR2` writer
4pub type W = crate::W<EXTICR2rs>;
5///EXTI4 configuration
6pub use super::exticr1::EXTI0;
7///Field `EXTI4` reader - EXTI4 configuration
8pub use super::exticr1::EXTI0_R as EXTI4_R;
9///Field `EXTI5` reader - EXTI5 configuration
10pub use super::exticr1::EXTI0_R as EXTI5_R;
11///Field `EXTI6` reader - EXTI6 configuration
12pub use super::exticr1::EXTI0_R as EXTI6_R;
13///Field `EXTI7` reader - EXTI7 configuration
14pub use super::exticr1::EXTI0_R as EXTI7_R;
15///Field `EXTI4` writer - EXTI4 configuration
16pub use super::exticr1::EXTI0_W as EXTI4_W;
17///Field `EXTI5` writer - EXTI5 configuration
18pub use super::exticr1::EXTI0_W as EXTI5_W;
19///Field `EXTI6` writer - EXTI6 configuration
20pub use super::exticr1::EXTI0_W as EXTI6_W;
21///Field `EXTI7` writer - EXTI7 configuration
22pub use super::exticr1::EXTI0_W as EXTI7_W;
23impl R {
24    ///Bits 0:3 - EXTI4 configuration
25    #[inline(always)]
26    pub fn exti4(&self) -> EXTI4_R {
27        EXTI4_R::new((self.bits & 0x0f) as u8)
28    }
29    ///Bits 4:7 - EXTI5 configuration
30    #[inline(always)]
31    pub fn exti5(&self) -> EXTI5_R {
32        EXTI5_R::new(((self.bits >> 4) & 0x0f) as u8)
33    }
34    ///Bits 8:11 - EXTI6 configuration
35    #[inline(always)]
36    pub fn exti6(&self) -> EXTI6_R {
37        EXTI6_R::new(((self.bits >> 8) & 0x0f) as u8)
38    }
39    ///Bits 12:15 - EXTI7 configuration
40    #[inline(always)]
41    pub fn exti7(&self) -> EXTI7_R {
42        EXTI7_R::new(((self.bits >> 12) & 0x0f) as u8)
43    }
44}
45impl core::fmt::Debug for R {
46    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
47        f.debug_struct("EXTICR2")
48            .field("exti4", &self.exti4())
49            .field("exti5", &self.exti5())
50            .field("exti6", &self.exti6())
51            .field("exti7", &self.exti7())
52            .finish()
53    }
54}
55impl W {
56    ///Bits 0:3 - EXTI4 configuration
57    #[inline(always)]
58    pub fn exti4(&mut self) -> EXTI4_W<EXTICR2rs> {
59        EXTI4_W::new(self, 0)
60    }
61    ///Bits 4:7 - EXTI5 configuration
62    #[inline(always)]
63    pub fn exti5(&mut self) -> EXTI5_W<EXTICR2rs> {
64        EXTI5_W::new(self, 4)
65    }
66    ///Bits 8:11 - EXTI6 configuration
67    #[inline(always)]
68    pub fn exti6(&mut self) -> EXTI6_W<EXTICR2rs> {
69        EXTI6_W::new(self, 8)
70    }
71    ///Bits 12:15 - EXTI7 configuration
72    #[inline(always)]
73    pub fn exti7(&mut self) -> EXTI7_W<EXTICR2rs> {
74        EXTI7_W::new(self, 12)
75    }
76}
77/**External interrupt configuration register 2 (AFIO_EXTICR2)
78
79You can [`read`](crate::Reg::read) this register and get [`exticr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#AFIO:EXTICR2)*/
82pub struct EXTICR2rs;
83impl crate::RegisterSpec for EXTICR2rs {
84    type Ux = u32;
85}
86///`read()` method returns [`exticr2::R`](R) reader structure
87impl crate::Readable for EXTICR2rs {}
88///`write(|w| ..)` method takes [`exticr2::W`](W) writer structure
89impl crate::Writable for EXTICR2rs {
90    type Safety = crate::Unsafe;
91}
92///`reset()` method sets EXTICR2 to value 0
93impl crate::Resettable for EXTICR2rs {}
stm32f1_staging/stm32f101/afio/exticr2.rs

stm32f1_staging/stm32f101/afio/
exticr2.rs
