stm32f1_staging/stm32f101/adc3/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5///Field `AWDCH` reader - Analog watchdog channel select bits
6pub type AWDCH_R = crate::FieldReader;
7///Field `AWDCH` writer - Analog watchdog channel select bits
8pub type AWDCH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9///Analog watchdog interrupt enable
10pub use crate::stm32f101::adc1::cr1::AWDIE;
11///Field `AWDIE` reader - Analog watchdog interrupt enable
12pub use crate::stm32f101::adc1::cr1::AWDIE_R;
13///Field `AWDIE` writer - Analog watchdog interrupt enable
14pub use crate::stm32f101::adc1::cr1::AWDIE_W;
15///Enable the watchdog on a single channel in scan mode
16pub use crate::stm32f101::adc1::cr1::AWDSGL;
17///Field `AWDSGL` reader - Enable the watchdog on a single channel in scan mode
18pub use crate::stm32f101::adc1::cr1::AWDSGL_R;
19///Field `AWDSGL` writer - Enable the watchdog on a single channel in scan mode
20pub use crate::stm32f101::adc1::cr1::AWDSGL_W;
21///Discontinuous mode on regular channels
22pub use crate::stm32f101::adc1::cr1::DISCEN;
23///Field `DISCEN` reader - Discontinuous mode on regular channels
24pub use crate::stm32f101::adc1::cr1::DISCEN_R;
25///Field `DISCEN` writer - Discontinuous mode on regular channels
26pub use crate::stm32f101::adc1::cr1::DISCEN_W;
27///Interrupt enable for EOC
28pub use crate::stm32f101::adc1::cr1::EOCIE;
29///Field `EOCIE` reader - Interrupt enable for EOC
30pub use crate::stm32f101::adc1::cr1::EOCIE_R;
31///Field `EOCIE` writer - Interrupt enable for EOC
32pub use crate::stm32f101::adc1::cr1::EOCIE_W;
33///Automatic injected group conversion
34pub use crate::stm32f101::adc1::cr1::JAUTO;
35///Field `JAUTO` reader - Automatic injected group conversion
36pub use crate::stm32f101::adc1::cr1::JAUTO_R;
37///Field `JAUTO` writer - Automatic injected group conversion
38pub use crate::stm32f101::adc1::cr1::JAUTO_W;
39///Discontinuous mode on injected channels
40pub use crate::stm32f101::adc1::cr1::JDISCEN;
41///Field `JDISCEN` reader - Discontinuous mode on injected channels
42pub use crate::stm32f101::adc1::cr1::JDISCEN_R;
43///Field `JDISCEN` writer - Discontinuous mode on injected channels
44pub use crate::stm32f101::adc1::cr1::JDISCEN_W;
45///Interrupt enable for injected channels
46pub use crate::stm32f101::adc1::cr1::JEOCIE;
47///Field `JEOCIE` reader - Interrupt enable for injected channels
48pub use crate::stm32f101::adc1::cr1::JEOCIE_R;
49///Field `JEOCIE` writer - Interrupt enable for injected channels
50pub use crate::stm32f101::adc1::cr1::JEOCIE_W;
51///Scan mode
52pub use crate::stm32f101::adc1::cr1::SCAN;
53///Field `SCAN` reader - Scan mode
54pub use crate::stm32f101::adc1::cr1::SCAN_R;
55///Field `SCAN` writer - Scan mode
56pub use crate::stm32f101::adc1::cr1::SCAN_W;
57///Field `DISCNUM` reader - Discontinuous mode channel count
58pub type DISCNUM_R = crate::FieldReader;
59///Field `DISCNUM` writer - Discontinuous mode channel count
60pub type DISCNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
61///Analog watchdog enable on regular channels
62pub use crate::stm32f101::adc1::cr1::AWDEN;
63///Field `AWDEN` reader - Analog watchdog enable on regular channels
64pub use crate::stm32f101::adc1::cr1::AWDEN_R;
65///Field `AWDEN` writer - Analog watchdog enable on regular channels
66pub use crate::stm32f101::adc1::cr1::AWDEN_W;
67///Analog watchdog enable on injected channels
68pub use crate::stm32f101::adc1::cr1::JAWDEN;
69///Field `JAWDEN` reader - Analog watchdog enable on injected channels
70pub use crate::stm32f101::adc1::cr1::JAWDEN_R;
71///Field `JAWDEN` writer - Analog watchdog enable on injected channels
72pub use crate::stm32f101::adc1::cr1::JAWDEN_W;
73impl R {
74    ///Bits 0:4 - Analog watchdog channel select bits
75    #[inline(always)]
76    pub fn awdch(&self) -> AWDCH_R {
77        AWDCH_R::new((self.bits & 0x1f) as u8)
78    }
79    ///Bit 5 - Interrupt enable for EOC
80    #[inline(always)]
81    pub fn eocie(&self) -> EOCIE_R {
82        EOCIE_R::new(((self.bits >> 5) & 1) != 0)
83    }
84    ///Bit 6 - Analog watchdog interrupt enable
85    #[inline(always)]
86    pub fn awdie(&self) -> AWDIE_R {
87        AWDIE_R::new(((self.bits >> 6) & 1) != 0)
88    }
89    ///Bit 7 - Interrupt enable for injected channels
90    #[inline(always)]
91    pub fn jeocie(&self) -> JEOCIE_R {
92        JEOCIE_R::new(((self.bits >> 7) & 1) != 0)
93    }
94    ///Bit 8 - Scan mode
95    #[inline(always)]
96    pub fn scan(&self) -> SCAN_R {
97        SCAN_R::new(((self.bits >> 8) & 1) != 0)
98    }
99    ///Bit 9 - Enable the watchdog on a single channel in scan mode
100    #[inline(always)]
101    pub fn awdsgl(&self) -> AWDSGL_R {
102        AWDSGL_R::new(((self.bits >> 9) & 1) != 0)
103    }
104    ///Bit 10 - Automatic injected group conversion
105    #[inline(always)]
106    pub fn jauto(&self) -> JAUTO_R {
107        JAUTO_R::new(((self.bits >> 10) & 1) != 0)
108    }
109    ///Bit 11 - Discontinuous mode on regular channels
110    #[inline(always)]
111    pub fn discen(&self) -> DISCEN_R {
112        DISCEN_R::new(((self.bits >> 11) & 1) != 0)
113    }
114    ///Bit 12 - Discontinuous mode on injected channels
115    #[inline(always)]
116    pub fn jdiscen(&self) -> JDISCEN_R {
117        JDISCEN_R::new(((self.bits >> 12) & 1) != 0)
118    }
119    ///Bits 13:15 - Discontinuous mode channel count
120    #[inline(always)]
121    pub fn discnum(&self) -> DISCNUM_R {
122        DISCNUM_R::new(((self.bits >> 13) & 7) as u8)
123    }
124    ///Bit 22 - Analog watchdog enable on injected channels
125    #[inline(always)]
126    pub fn jawden(&self) -> JAWDEN_R {
127        JAWDEN_R::new(((self.bits >> 22) & 1) != 0)
128    }
129    ///Bit 23 - Analog watchdog enable on regular channels
130    #[inline(always)]
131    pub fn awden(&self) -> AWDEN_R {
132        AWDEN_R::new(((self.bits >> 23) & 1) != 0)
133    }
134}
135impl core::fmt::Debug for R {
136    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
137        f.debug_struct("CR1")
138            .field("awden", &self.awden())
139            .field("jawden", &self.jawden())
140            .field("discnum", &self.discnum())
141            .field("jdiscen", &self.jdiscen())
142            .field("discen", &self.discen())
143            .field("jauto", &self.jauto())
144            .field("awdsgl", &self.awdsgl())
145            .field("scan", &self.scan())
146            .field("jeocie", &self.jeocie())
147            .field("awdie", &self.awdie())
148            .field("eocie", &self.eocie())
149            .field("awdch", &self.awdch())
150            .finish()
151    }
152}
153impl W {
154    ///Bits 0:4 - Analog watchdog channel select bits
155    #[inline(always)]
156    pub fn awdch(&mut self) -> AWDCH_W<CR1rs> {
157        AWDCH_W::new(self, 0)
158    }
159    ///Bit 5 - Interrupt enable for EOC
160    #[inline(always)]
161    pub fn eocie(&mut self) -> EOCIE_W<CR1rs> {
162        EOCIE_W::new(self, 5)
163    }
164    ///Bit 6 - Analog watchdog interrupt enable
165    #[inline(always)]
166    pub fn awdie(&mut self) -> AWDIE_W<CR1rs> {
167        AWDIE_W::new(self, 6)
168    }
169    ///Bit 7 - Interrupt enable for injected channels
170    #[inline(always)]
171    pub fn jeocie(&mut self) -> JEOCIE_W<CR1rs> {
172        JEOCIE_W::new(self, 7)
173    }
174    ///Bit 8 - Scan mode
175    #[inline(always)]
176    pub fn scan(&mut self) -> SCAN_W<CR1rs> {
177        SCAN_W::new(self, 8)
178    }
179    ///Bit 9 - Enable the watchdog on a single channel in scan mode
180    #[inline(always)]
181    pub fn awdsgl(&mut self) -> AWDSGL_W<CR1rs> {
182        AWDSGL_W::new(self, 9)
183    }
184    ///Bit 10 - Automatic injected group conversion
185    #[inline(always)]
186    pub fn jauto(&mut self) -> JAUTO_W<CR1rs> {
187        JAUTO_W::new(self, 10)
188    }
189    ///Bit 11 - Discontinuous mode on regular channels
190    #[inline(always)]
191    pub fn discen(&mut self) -> DISCEN_W<CR1rs> {
192        DISCEN_W::new(self, 11)
193    }
194    ///Bit 12 - Discontinuous mode on injected channels
195    #[inline(always)]
196    pub fn jdiscen(&mut self) -> JDISCEN_W<CR1rs> {
197        JDISCEN_W::new(self, 12)
198    }
199    ///Bits 13:15 - Discontinuous mode channel count
200    #[inline(always)]
201    pub fn discnum(&mut self) -> DISCNUM_W<CR1rs> {
202        DISCNUM_W::new(self, 13)
203    }
204    ///Bit 22 - Analog watchdog enable on injected channels
205    #[inline(always)]
206    pub fn jawden(&mut self) -> JAWDEN_W<CR1rs> {
207        JAWDEN_W::new(self, 22)
208    }
209    ///Bit 23 - Analog watchdog enable on regular channels
210    #[inline(always)]
211    pub fn awden(&mut self) -> AWDEN_W<CR1rs> {
212        AWDEN_W::new(self, 23)
213    }
214}
215/**control register 1
216
217You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
218
219See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC3:CR1)*/
220pub struct CR1rs;
221impl crate::RegisterSpec for CR1rs {
222    type Ux = u32;
223}
224///`read()` method returns [`cr1::R`](R) reader structure
225impl crate::Readable for CR1rs {}
226///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
227impl crate::Writable for CR1rs {
228    type Safety = crate::Unsafe;
229}
230///`reset()` method sets CR1 to value 0
231impl crate::Resettable for CR1rs {}
stm32f1_staging/stm32f101/adc3/cr1.rs

stm32f1_staging/stm32f101/adc3/
cr1.rs
