stm32f1_staging/stm32f101/adc1/
sqr1.rs

1///Register `SQR1` reader
2pub type R = crate::R<SQR1rs>;
3///Register `SQR1` writer
4pub type W = crate::W<SQR1rs>;
5///Field `SQ(13-16)` reader - %s conversion in regular sequence
6pub type SQ_R = crate::FieldReader;
7///Field `SQ(13-16)` writer - %s conversion in regular sequence
8pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9///Field `L` reader - Regular channel sequence length
10pub type L_R = crate::FieldReader;
11///Field `L` writer - Regular channel sequence length
12pub type L_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
13impl R {
14    ///(13-16) conversion in regular sequence
15    ///
16    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ13` field.</div>
17    #[inline(always)]
18    pub fn sq(&self, n: u8) -> SQ_R {
19        #[allow(clippy::no_effect)] [(); 4][n as usize];
20        SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8)
21    }
22    ///Iterator for array of:
23    ///(13-16) conversion in regular sequence
24    #[inline(always)]
25    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
26        (0..4).map(move |n| SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8))
27    }
28    ///Bits 0:4 - 13 conversion in regular sequence
29    #[inline(always)]
30    pub fn sq13(&self) -> SQ_R {
31        SQ_R::new((self.bits & 0x1f) as u8)
32    }
33    ///Bits 5:9 - 14 conversion in regular sequence
34    #[inline(always)]
35    pub fn sq14(&self) -> SQ_R {
36        SQ_R::new(((self.bits >> 5) & 0x1f) as u8)
37    }
38    ///Bits 10:14 - 15 conversion in regular sequence
39    #[inline(always)]
40    pub fn sq15(&self) -> SQ_R {
41        SQ_R::new(((self.bits >> 10) & 0x1f) as u8)
42    }
43    ///Bits 15:19 - 16 conversion in regular sequence
44    #[inline(always)]
45    pub fn sq16(&self) -> SQ_R {
46        SQ_R::new(((self.bits >> 15) & 0x1f) as u8)
47    }
48    ///Bits 20:23 - Regular channel sequence length
49    #[inline(always)]
50    pub fn l(&self) -> L_R {
51        L_R::new(((self.bits >> 20) & 0x0f) as u8)
52    }
53}
54impl core::fmt::Debug for R {
55    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
56        f.debug_struct("SQR1")
57            .field("l", &self.l())
58            .field("sq13", &self.sq13())
59            .field("sq14", &self.sq14())
60            .field("sq15", &self.sq15())
61            .field("sq16", &self.sq16())
62            .finish()
63    }
64}
65impl W {
66    ///(13-16) conversion in regular sequence
67    ///
68    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ13` field.</div>
69    #[inline(always)]
70    pub fn sq(&mut self, n: u8) -> SQ_W<SQR1rs> {
71        #[allow(clippy::no_effect)] [(); 4][n as usize];
72        SQ_W::new(self, n * 5)
73    }
74    ///Bits 0:4 - 13 conversion in regular sequence
75    #[inline(always)]
76    pub fn sq13(&mut self) -> SQ_W<SQR1rs> {
77        SQ_W::new(self, 0)
78    }
79    ///Bits 5:9 - 14 conversion in regular sequence
80    #[inline(always)]
81    pub fn sq14(&mut self) -> SQ_W<SQR1rs> {
82        SQ_W::new(self, 5)
83    }
84    ///Bits 10:14 - 15 conversion in regular sequence
85    #[inline(always)]
86    pub fn sq15(&mut self) -> SQ_W<SQR1rs> {
87        SQ_W::new(self, 10)
88    }
89    ///Bits 15:19 - 16 conversion in regular sequence
90    #[inline(always)]
91    pub fn sq16(&mut self) -> SQ_W<SQR1rs> {
92        SQ_W::new(self, 15)
93    }
94    ///Bits 20:23 - Regular channel sequence length
95    #[inline(always)]
96    pub fn l(&mut self) -> L_W<SQR1rs> {
97        L_W::new(self, 20)
98    }
99}
100/**regular sequence register 1
101
102You can [`read`](crate::Reg::read) this register and get [`sqr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC1:SQR1)*/
105pub struct SQR1rs;
106impl crate::RegisterSpec for SQR1rs {
107    type Ux = u32;
108}
109///`read()` method returns [`sqr1::R`](R) reader structure
110impl crate::Readable for SQR1rs {}
111///`write(|w| ..)` method takes [`sqr1::W`](W) writer structure
112impl crate::Writable for SQR1rs {
113    type Safety = crate::Unsafe;
114}
115///`reset()` method sets SQR1 to value 0
116impl crate::Resettable for SQR1rs {}
stm32f1_staging/stm32f101/adc1/sqr1.rs

stm32f1_staging/stm32f101/adc1/
sqr1.rs
