stm32f1_staging/stm32f101/adc1/
smpr2.rs

1///Register `SMPR2` reader
2pub type R = crate::R<SMPR2rs>;
3///Register `SMPR2` writer
4pub type W = crate::W<SMPR2rs>;
5///Channel %s sample time selection
6pub use super::smpr1::SMP10;
7///Field `SMP(0-9)` reader - Channel %s sample time selection
8pub use super::smpr1::SMP_R;
9///Field `SMP(0-9)` writer - Channel %s sample time selection
10pub use super::smpr1::SMP_W;
11impl R {
12    ///Channel (0-9) sample time selection
13    ///
14    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP0` field.</div>
15    #[inline(always)]
16    pub fn smp(&self, n: u8) -> SMP_R {
17        #[allow(clippy::no_effect)] [(); 10][n as usize];
18        SMP_R::new(((self.bits >> (n * 3)) & 7) as u8)
19    }
20    ///Iterator for array of:
21    ///Channel (0-9) sample time selection
22    #[inline(always)]
23    pub fn smp_iter(&self) -> impl Iterator<Item = SMP_R> + '_ {
24        (0..10).map(move |n| SMP_R::new(((self.bits >> (n * 3)) & 7) as u8))
25    }
26    ///Bits 0:2 - Channel 0 sample time selection
27    #[inline(always)]
28    pub fn smp0(&self) -> SMP_R {
29        SMP_R::new((self.bits & 7) as u8)
30    }
31    ///Bits 3:5 - Channel 1 sample time selection
32    #[inline(always)]
33    pub fn smp1(&self) -> SMP_R {
34        SMP_R::new(((self.bits >> 3) & 7) as u8)
35    }
36    ///Bits 6:8 - Channel 2 sample time selection
37    #[inline(always)]
38    pub fn smp2(&self) -> SMP_R {
39        SMP_R::new(((self.bits >> 6) & 7) as u8)
40    }
41    ///Bits 9:11 - Channel 3 sample time selection
42    #[inline(always)]
43    pub fn smp3(&self) -> SMP_R {
44        SMP_R::new(((self.bits >> 9) & 7) as u8)
45    }
46    ///Bits 12:14 - Channel 4 sample time selection
47    #[inline(always)]
48    pub fn smp4(&self) -> SMP_R {
49        SMP_R::new(((self.bits >> 12) & 7) as u8)
50    }
51    ///Bits 15:17 - Channel 5 sample time selection
52    #[inline(always)]
53    pub fn smp5(&self) -> SMP_R {
54        SMP_R::new(((self.bits >> 15) & 7) as u8)
55    }
56    ///Bits 18:20 - Channel 6 sample time selection
57    #[inline(always)]
58    pub fn smp6(&self) -> SMP_R {
59        SMP_R::new(((self.bits >> 18) & 7) as u8)
60    }
61    ///Bits 21:23 - Channel 7 sample time selection
62    #[inline(always)]
63    pub fn smp7(&self) -> SMP_R {
64        SMP_R::new(((self.bits >> 21) & 7) as u8)
65    }
66    ///Bits 24:26 - Channel 8 sample time selection
67    #[inline(always)]
68    pub fn smp8(&self) -> SMP_R {
69        SMP_R::new(((self.bits >> 24) & 7) as u8)
70    }
71    ///Bits 27:29 - Channel 9 sample time selection
72    #[inline(always)]
73    pub fn smp9(&self) -> SMP_R {
74        SMP_R::new(((self.bits >> 27) & 7) as u8)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("SMPR2")
80            .field("smp0", &self.smp0())
81            .field("smp1", &self.smp1())
82            .field("smp2", &self.smp2())
83            .field("smp3", &self.smp3())
84            .field("smp4", &self.smp4())
85            .field("smp5", &self.smp5())
86            .field("smp6", &self.smp6())
87            .field("smp7", &self.smp7())
88            .field("smp8", &self.smp8())
89            .field("smp9", &self.smp9())
90            .finish()
91    }
92}
93impl W {
94    ///Channel (0-9) sample time selection
95    ///
96    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SMP0` field.</div>
97    #[inline(always)]
98    pub fn smp(&mut self, n: u8) -> SMP_W<SMPR2rs> {
99        #[allow(clippy::no_effect)] [(); 10][n as usize];
100        SMP_W::new(self, n * 3)
101    }
102    ///Bits 0:2 - Channel 0 sample time selection
103    #[inline(always)]
104    pub fn smp0(&mut self) -> SMP_W<SMPR2rs> {
105        SMP_W::new(self, 0)
106    }
107    ///Bits 3:5 - Channel 1 sample time selection
108    #[inline(always)]
109    pub fn smp1(&mut self) -> SMP_W<SMPR2rs> {
110        SMP_W::new(self, 3)
111    }
112    ///Bits 6:8 - Channel 2 sample time selection
113    #[inline(always)]
114    pub fn smp2(&mut self) -> SMP_W<SMPR2rs> {
115        SMP_W::new(self, 6)
116    }
117    ///Bits 9:11 - Channel 3 sample time selection
118    #[inline(always)]
119    pub fn smp3(&mut self) -> SMP_W<SMPR2rs> {
120        SMP_W::new(self, 9)
121    }
122    ///Bits 12:14 - Channel 4 sample time selection
123    #[inline(always)]
124    pub fn smp4(&mut self) -> SMP_W<SMPR2rs> {
125        SMP_W::new(self, 12)
126    }
127    ///Bits 15:17 - Channel 5 sample time selection
128    #[inline(always)]
129    pub fn smp5(&mut self) -> SMP_W<SMPR2rs> {
130        SMP_W::new(self, 15)
131    }
132    ///Bits 18:20 - Channel 6 sample time selection
133    #[inline(always)]
134    pub fn smp6(&mut self) -> SMP_W<SMPR2rs> {
135        SMP_W::new(self, 18)
136    }
137    ///Bits 21:23 - Channel 7 sample time selection
138    #[inline(always)]
139    pub fn smp7(&mut self) -> SMP_W<SMPR2rs> {
140        SMP_W::new(self, 21)
141    }
142    ///Bits 24:26 - Channel 8 sample time selection
143    #[inline(always)]
144    pub fn smp8(&mut self) -> SMP_W<SMPR2rs> {
145        SMP_W::new(self, 24)
146    }
147    ///Bits 27:29 - Channel 9 sample time selection
148    #[inline(always)]
149    pub fn smp9(&mut self) -> SMP_W<SMPR2rs> {
150        SMP_W::new(self, 27)
151    }
152}
153/**sample time register 2
154
155You can [`read`](crate::Reg::read) this register and get [`smpr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC1:SMPR2)*/
158pub struct SMPR2rs;
159impl crate::RegisterSpec for SMPR2rs {
160    type Ux = u32;
161}
162///`read()` method returns [`smpr2::R`](R) reader structure
163impl crate::Readable for SMPR2rs {}
164///`write(|w| ..)` method takes [`smpr2::W`](W) writer structure
165impl crate::Writable for SMPR2rs {
166    type Safety = crate::Unsafe;
167}
168///`reset()` method sets SMPR2 to value 0
169impl crate::Resettable for SMPR2rs {}
stm32f1_staging/stm32f101/adc1/smpr2.rs

stm32f1_staging/stm32f101/adc1/
smpr2.rs
