stm32f1_staging/stm32f100/usart1/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**Send break
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum SBK {
11    ///0: No break character is transmitted
12    NoBreak = 0,
13    ///1: Break character transmitted
14    Break = 1,
15}
16impl From<SBK> for bool {
17    #[inline(always)]
18    fn from(variant: SBK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `SBK` reader - Send break
23pub type SBK_R = crate::BitReader<SBK>;
24impl SBK_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> SBK {
28        match self.bits {
29            false => SBK::NoBreak,
30            true => SBK::Break,
31        }
32    }
33    ///No break character is transmitted
34    #[inline(always)]
35    pub fn is_no_break(&self) -> bool {
36        *self == SBK::NoBreak
37    }
38    ///Break character transmitted
39    #[inline(always)]
40    pub fn is_break(&self) -> bool {
41        *self == SBK::Break
42    }
43}
44///Field `SBK` writer - Send break
45pub type SBK_W<'a, REG> = crate::BitWriter<'a, REG, SBK>;
46impl<'a, REG> SBK_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///No break character is transmitted
51    #[inline(always)]
52    pub fn no_break(self) -> &'a mut crate::W<REG> {
53        self.variant(SBK::NoBreak)
54    }
55    ///Break character transmitted
56    #[inline(always)]
57    pub fn break_(self) -> &'a mut crate::W<REG> {
58        self.variant(SBK::Break)
59    }
60}
61/**Receiver wakeup
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RWU {
67    ///0: Receiver in active mode
68    Active = 0,
69    ///1: Receiver in mute mode
70    Mute = 1,
71}
72impl From<RWU> for bool {
73    #[inline(always)]
74    fn from(variant: RWU) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `RWU` reader - Receiver wakeup
79pub type RWU_R = crate::BitReader<RWU>;
80impl RWU_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> RWU {
84        match self.bits {
85            false => RWU::Active,
86            true => RWU::Mute,
87        }
88    }
89    ///Receiver in active mode
90    #[inline(always)]
91    pub fn is_active(&self) -> bool {
92        *self == RWU::Active
93    }
94    ///Receiver in mute mode
95    #[inline(always)]
96    pub fn is_mute(&self) -> bool {
97        *self == RWU::Mute
98    }
99}
100///Field `RWU` writer - Receiver wakeup
101pub type RWU_W<'a, REG> = crate::BitWriter<'a, REG, RWU>;
102impl<'a, REG> RWU_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Receiver in active mode
107    #[inline(always)]
108    pub fn active(self) -> &'a mut crate::W<REG> {
109        self.variant(RWU::Active)
110    }
111    ///Receiver in mute mode
112    #[inline(always)]
113    pub fn mute(self) -> &'a mut crate::W<REG> {
114        self.variant(RWU::Mute)
115    }
116}
117/**Receiver enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum RE {
123    ///0: Receiver disabled
124    Disabled = 0,
125    ///1: Receiver enabled
126    Enabled = 1,
127}
128impl From<RE> for bool {
129    #[inline(always)]
130    fn from(variant: RE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `RE` reader - Receiver enable
135pub type RE_R = crate::BitReader<RE>;
136impl RE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> RE {
140        match self.bits {
141            false => RE::Disabled,
142            true => RE::Enabled,
143        }
144    }
145    ///Receiver disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == RE::Disabled
149    }
150    ///Receiver enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == RE::Enabled
154    }
155}
156///Field `RE` writer - Receiver enable
157pub type RE_W<'a, REG> = crate::BitWriter<'a, REG, RE>;
158impl<'a, REG> RE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Receiver disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(RE::Disabled)
166    }
167    ///Receiver enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(RE::Enabled)
171    }
172}
173/**Transmitter enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum TE {
179    ///0: Transmitter disabled
180    Disabled = 0,
181    ///1: Transmitter enabled
182    Enabled = 1,
183}
184impl From<TE> for bool {
185    #[inline(always)]
186    fn from(variant: TE) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `TE` reader - Transmitter enable
191pub type TE_R = crate::BitReader<TE>;
192impl TE_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> TE {
196        match self.bits {
197            false => TE::Disabled,
198            true => TE::Enabled,
199        }
200    }
201    ///Transmitter disabled
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == TE::Disabled
205    }
206    ///Transmitter enabled
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == TE::Enabled
210    }
211}
212///Field `TE` writer - Transmitter enable
213pub type TE_W<'a, REG> = crate::BitWriter<'a, REG, TE>;
214impl<'a, REG> TE_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Transmitter disabled
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(TE::Disabled)
222    }
223    ///Transmitter enabled
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(TE::Enabled)
227    }
228}
229/**IDLE interrupt enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum IDLEIE {
235    ///0: IDLE interrupt disabled
236    Disabled = 0,
237    ///1: IDLE interrupt enabled
238    Enabled = 1,
239}
240impl From<IDLEIE> for bool {
241    #[inline(always)]
242    fn from(variant: IDLEIE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `IDLEIE` reader - IDLE interrupt enable
247pub type IDLEIE_R = crate::BitReader<IDLEIE>;
248impl IDLEIE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> IDLEIE {
252        match self.bits {
253            false => IDLEIE::Disabled,
254            true => IDLEIE::Enabled,
255        }
256    }
257    ///IDLE interrupt disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == IDLEIE::Disabled
261    }
262    ///IDLE interrupt enabled
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == IDLEIE::Enabled
266    }
267}
268///Field `IDLEIE` writer - IDLE interrupt enable
269pub type IDLEIE_W<'a, REG> = crate::BitWriter<'a, REG, IDLEIE>;
270impl<'a, REG> IDLEIE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///IDLE interrupt disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(IDLEIE::Disabled)
278    }
279    ///IDLE interrupt enabled
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(IDLEIE::Enabled)
283    }
284}
285/**RXNE interrupt enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum RXNEIE {
291    ///0: RXNE interrupt disabled
292    Disabled = 0,
293    ///1: RXNE interrupt enabled
294    Enabled = 1,
295}
296impl From<RXNEIE> for bool {
297    #[inline(always)]
298    fn from(variant: RXNEIE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `RXNEIE` reader - RXNE interrupt enable
303pub type RXNEIE_R = crate::BitReader<RXNEIE>;
304impl RXNEIE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> RXNEIE {
308        match self.bits {
309            false => RXNEIE::Disabled,
310            true => RXNEIE::Enabled,
311        }
312    }
313    ///RXNE interrupt disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == RXNEIE::Disabled
317    }
318    ///RXNE interrupt enabled
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == RXNEIE::Enabled
322    }
323}
324///Field `RXNEIE` writer - RXNE interrupt enable
325pub type RXNEIE_W<'a, REG> = crate::BitWriter<'a, REG, RXNEIE>;
326impl<'a, REG> RXNEIE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///RXNE interrupt disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(RXNEIE::Disabled)
334    }
335    ///RXNE interrupt enabled
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(RXNEIE::Enabled)
339    }
340}
341/**Transmission complete interrupt enable
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum TCIE {
347    ///0: TC interrupt disabled
348    Disabled = 0,
349    ///1: TC interrupt enabled
350    Enabled = 1,
351}
352impl From<TCIE> for bool {
353    #[inline(always)]
354    fn from(variant: TCIE) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `TCIE` reader - Transmission complete interrupt enable
359pub type TCIE_R = crate::BitReader<TCIE>;
360impl TCIE_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> TCIE {
364        match self.bits {
365            false => TCIE::Disabled,
366            true => TCIE::Enabled,
367        }
368    }
369    ///TC interrupt disabled
370    #[inline(always)]
371    pub fn is_disabled(&self) -> bool {
372        *self == TCIE::Disabled
373    }
374    ///TC interrupt enabled
375    #[inline(always)]
376    pub fn is_enabled(&self) -> bool {
377        *self == TCIE::Enabled
378    }
379}
380///Field `TCIE` writer - Transmission complete interrupt enable
381pub type TCIE_W<'a, REG> = crate::BitWriter<'a, REG, TCIE>;
382impl<'a, REG> TCIE_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///TC interrupt disabled
387    #[inline(always)]
388    pub fn disabled(self) -> &'a mut crate::W<REG> {
389        self.variant(TCIE::Disabled)
390    }
391    ///TC interrupt enabled
392    #[inline(always)]
393    pub fn enabled(self) -> &'a mut crate::W<REG> {
394        self.variant(TCIE::Enabled)
395    }
396}
397/**TXE interrupt enable
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum TXEIE {
403    ///0: TXE interrupt disabled
404    Disabled = 0,
405    ///1: TXE interrupt enabled
406    Enabled = 1,
407}
408impl From<TXEIE> for bool {
409    #[inline(always)]
410    fn from(variant: TXEIE) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `TXEIE` reader - TXE interrupt enable
415pub type TXEIE_R = crate::BitReader<TXEIE>;
416impl TXEIE_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> TXEIE {
420        match self.bits {
421            false => TXEIE::Disabled,
422            true => TXEIE::Enabled,
423        }
424    }
425    ///TXE interrupt disabled
426    #[inline(always)]
427    pub fn is_disabled(&self) -> bool {
428        *self == TXEIE::Disabled
429    }
430    ///TXE interrupt enabled
431    #[inline(always)]
432    pub fn is_enabled(&self) -> bool {
433        *self == TXEIE::Enabled
434    }
435}
436///Field `TXEIE` writer - TXE interrupt enable
437pub type TXEIE_W<'a, REG> = crate::BitWriter<'a, REG, TXEIE>;
438impl<'a, REG> TXEIE_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///TXE interrupt disabled
443    #[inline(always)]
444    pub fn disabled(self) -> &'a mut crate::W<REG> {
445        self.variant(TXEIE::Disabled)
446    }
447    ///TXE interrupt enabled
448    #[inline(always)]
449    pub fn enabled(self) -> &'a mut crate::W<REG> {
450        self.variant(TXEIE::Enabled)
451    }
452}
453/**PE interrupt enable
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458pub enum PEIE {
459    ///0: PE interrupt disabled
460    Disabled = 0,
461    ///1: PE interrupt enabled
462    Enabled = 1,
463}
464impl From<PEIE> for bool {
465    #[inline(always)]
466    fn from(variant: PEIE) -> Self {
467        variant as u8 != 0
468    }
469}
470///Field `PEIE` reader - PE interrupt enable
471pub type PEIE_R = crate::BitReader<PEIE>;
472impl PEIE_R {
473    ///Get enumerated values variant
474    #[inline(always)]
475    pub const fn variant(&self) -> PEIE {
476        match self.bits {
477            false => PEIE::Disabled,
478            true => PEIE::Enabled,
479        }
480    }
481    ///PE interrupt disabled
482    #[inline(always)]
483    pub fn is_disabled(&self) -> bool {
484        *self == PEIE::Disabled
485    }
486    ///PE interrupt enabled
487    #[inline(always)]
488    pub fn is_enabled(&self) -> bool {
489        *self == PEIE::Enabled
490    }
491}
492///Field `PEIE` writer - PE interrupt enable
493pub type PEIE_W<'a, REG> = crate::BitWriter<'a, REG, PEIE>;
494impl<'a, REG> PEIE_W<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497{
498    ///PE interrupt disabled
499    #[inline(always)]
500    pub fn disabled(self) -> &'a mut crate::W<REG> {
501        self.variant(PEIE::Disabled)
502    }
503    ///PE interrupt enabled
504    #[inline(always)]
505    pub fn enabled(self) -> &'a mut crate::W<REG> {
506        self.variant(PEIE::Enabled)
507    }
508}
509/**Parity selection
510
511Value on reset: 0*/
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum PS {
515    ///0: Even parity
516    Even = 0,
517    ///1: Odd parity
518    Odd = 1,
519}
520impl From<PS> for bool {
521    #[inline(always)]
522    fn from(variant: PS) -> Self {
523        variant as u8 != 0
524    }
525}
526///Field `PS` reader - Parity selection
527pub type PS_R = crate::BitReader<PS>;
528impl PS_R {
529    ///Get enumerated values variant
530    #[inline(always)]
531    pub const fn variant(&self) -> PS {
532        match self.bits {
533            false => PS::Even,
534            true => PS::Odd,
535        }
536    }
537    ///Even parity
538    #[inline(always)]
539    pub fn is_even(&self) -> bool {
540        *self == PS::Even
541    }
542    ///Odd parity
543    #[inline(always)]
544    pub fn is_odd(&self) -> bool {
545        *self == PS::Odd
546    }
547}
548///Field `PS` writer - Parity selection
549pub type PS_W<'a, REG> = crate::BitWriter<'a, REG, PS>;
550impl<'a, REG> PS_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    ///Even parity
555    #[inline(always)]
556    pub fn even(self) -> &'a mut crate::W<REG> {
557        self.variant(PS::Even)
558    }
559    ///Odd parity
560    #[inline(always)]
561    pub fn odd(self) -> &'a mut crate::W<REG> {
562        self.variant(PS::Odd)
563    }
564}
565/**Parity control enable
566
567Value on reset: 0*/
568#[cfg_attr(feature = "defmt", derive(defmt::Format))]
569#[derive(Clone, Copy, Debug, PartialEq, Eq)]
570pub enum PCE {
571    ///0: Parity control disabled
572    Disabled = 0,
573    ///1: Parity control enabled
574    Enabled = 1,
575}
576impl From<PCE> for bool {
577    #[inline(always)]
578    fn from(variant: PCE) -> Self {
579        variant as u8 != 0
580    }
581}
582///Field `PCE` reader - Parity control enable
583pub type PCE_R = crate::BitReader<PCE>;
584impl PCE_R {
585    ///Get enumerated values variant
586    #[inline(always)]
587    pub const fn variant(&self) -> PCE {
588        match self.bits {
589            false => PCE::Disabled,
590            true => PCE::Enabled,
591        }
592    }
593    ///Parity control disabled
594    #[inline(always)]
595    pub fn is_disabled(&self) -> bool {
596        *self == PCE::Disabled
597    }
598    ///Parity control enabled
599    #[inline(always)]
600    pub fn is_enabled(&self) -> bool {
601        *self == PCE::Enabled
602    }
603}
604///Field `PCE` writer - Parity control enable
605pub type PCE_W<'a, REG> = crate::BitWriter<'a, REG, PCE>;
606impl<'a, REG> PCE_W<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609{
610    ///Parity control disabled
611    #[inline(always)]
612    pub fn disabled(self) -> &'a mut crate::W<REG> {
613        self.variant(PCE::Disabled)
614    }
615    ///Parity control enabled
616    #[inline(always)]
617    pub fn enabled(self) -> &'a mut crate::W<REG> {
618        self.variant(PCE::Enabled)
619    }
620}
621/**Wakeup method
622
623Value on reset: 0*/
624#[cfg_attr(feature = "defmt", derive(defmt::Format))]
625#[derive(Clone, Copy, Debug, PartialEq, Eq)]
626pub enum WAKE {
627    ///0: USART wakeup on idle line
628    IdleLine = 0,
629    ///1: USART wakeup on address mark
630    AddressMark = 1,
631}
632impl From<WAKE> for bool {
633    #[inline(always)]
634    fn from(variant: WAKE) -> Self {
635        variant as u8 != 0
636    }
637}
638///Field `WAKE` reader - Wakeup method
639pub type WAKE_R = crate::BitReader<WAKE>;
640impl WAKE_R {
641    ///Get enumerated values variant
642    #[inline(always)]
643    pub const fn variant(&self) -> WAKE {
644        match self.bits {
645            false => WAKE::IdleLine,
646            true => WAKE::AddressMark,
647        }
648    }
649    ///USART wakeup on idle line
650    #[inline(always)]
651    pub fn is_idle_line(&self) -> bool {
652        *self == WAKE::IdleLine
653    }
654    ///USART wakeup on address mark
655    #[inline(always)]
656    pub fn is_address_mark(&self) -> bool {
657        *self == WAKE::AddressMark
658    }
659}
660///Field `WAKE` writer - Wakeup method
661pub type WAKE_W<'a, REG> = crate::BitWriter<'a, REG, WAKE>;
662impl<'a, REG> WAKE_W<'a, REG>
663where
664    REG: crate::Writable + crate::RegisterSpec,
665{
666    ///USART wakeup on idle line
667    #[inline(always)]
668    pub fn idle_line(self) -> &'a mut crate::W<REG> {
669        self.variant(WAKE::IdleLine)
670    }
671    ///USART wakeup on address mark
672    #[inline(always)]
673    pub fn address_mark(self) -> &'a mut crate::W<REG> {
674        self.variant(WAKE::AddressMark)
675    }
676}
677/**Word length
678
679Value on reset: 0*/
680#[cfg_attr(feature = "defmt", derive(defmt::Format))]
681#[derive(Clone, Copy, Debug, PartialEq, Eq)]
682pub enum M {
683    ///0: 8 data bits
684    M8 = 0,
685    ///1: 9 data bits
686    M9 = 1,
687}
688impl From<M> for bool {
689    #[inline(always)]
690    fn from(variant: M) -> Self {
691        variant as u8 != 0
692    }
693}
694///Field `M` reader - Word length
695pub type M_R = crate::BitReader<M>;
696impl M_R {
697    ///Get enumerated values variant
698    #[inline(always)]
699    pub const fn variant(&self) -> M {
700        match self.bits {
701            false => M::M8,
702            true => M::M9,
703        }
704    }
705    ///8 data bits
706    #[inline(always)]
707    pub fn is_m8(&self) -> bool {
708        *self == M::M8
709    }
710    ///9 data bits
711    #[inline(always)]
712    pub fn is_m9(&self) -> bool {
713        *self == M::M9
714    }
715}
716///Field `M` writer - Word length
717pub type M_W<'a, REG> = crate::BitWriter<'a, REG, M>;
718impl<'a, REG> M_W<'a, REG>
719where
720    REG: crate::Writable + crate::RegisterSpec,
721{
722    ///8 data bits
723    #[inline(always)]
724    pub fn m8(self) -> &'a mut crate::W<REG> {
725        self.variant(M::M8)
726    }
727    ///9 data bits
728    #[inline(always)]
729    pub fn m9(self) -> &'a mut crate::W<REG> {
730        self.variant(M::M9)
731    }
732}
733/**USART enable
734
735Value on reset: 0*/
736#[cfg_attr(feature = "defmt", derive(defmt::Format))]
737#[derive(Clone, Copy, Debug, PartialEq, Eq)]
738pub enum UE {
739    ///0: USART prescaler and outputs disabled
740    Disabled = 0,
741    ///1: USART enabled
742    Enabled = 1,
743}
744impl From<UE> for bool {
745    #[inline(always)]
746    fn from(variant: UE) -> Self {
747        variant as u8 != 0
748    }
749}
750///Field `UE` reader - USART enable
751pub type UE_R = crate::BitReader<UE>;
752impl UE_R {
753    ///Get enumerated values variant
754    #[inline(always)]
755    pub const fn variant(&self) -> UE {
756        match self.bits {
757            false => UE::Disabled,
758            true => UE::Enabled,
759        }
760    }
761    ///USART prescaler and outputs disabled
762    #[inline(always)]
763    pub fn is_disabled(&self) -> bool {
764        *self == UE::Disabled
765    }
766    ///USART enabled
767    #[inline(always)]
768    pub fn is_enabled(&self) -> bool {
769        *self == UE::Enabled
770    }
771}
772///Field `UE` writer - USART enable
773pub type UE_W<'a, REG> = crate::BitWriter<'a, REG, UE>;
774impl<'a, REG> UE_W<'a, REG>
775where
776    REG: crate::Writable + crate::RegisterSpec,
777{
778    ///USART prescaler and outputs disabled
779    #[inline(always)]
780    pub fn disabled(self) -> &'a mut crate::W<REG> {
781        self.variant(UE::Disabled)
782    }
783    ///USART enabled
784    #[inline(always)]
785    pub fn enabled(self) -> &'a mut crate::W<REG> {
786        self.variant(UE::Enabled)
787    }
788}
789impl R {
790    ///Bit 0 - Send break
791    #[inline(always)]
792    pub fn sbk(&self) -> SBK_R {
793        SBK_R::new((self.bits & 1) != 0)
794    }
795    ///Bit 1 - Receiver wakeup
796    #[inline(always)]
797    pub fn rwu(&self) -> RWU_R {
798        RWU_R::new(((self.bits >> 1) & 1) != 0)
799    }
800    ///Bit 2 - Receiver enable
801    #[inline(always)]
802    pub fn re(&self) -> RE_R {
803        RE_R::new(((self.bits >> 2) & 1) != 0)
804    }
805    ///Bit 3 - Transmitter enable
806    #[inline(always)]
807    pub fn te(&self) -> TE_R {
808        TE_R::new(((self.bits >> 3) & 1) != 0)
809    }
810    ///Bit 4 - IDLE interrupt enable
811    #[inline(always)]
812    pub fn idleie(&self) -> IDLEIE_R {
813        IDLEIE_R::new(((self.bits >> 4) & 1) != 0)
814    }
815    ///Bit 5 - RXNE interrupt enable
816    #[inline(always)]
817    pub fn rxneie(&self) -> RXNEIE_R {
818        RXNEIE_R::new(((self.bits >> 5) & 1) != 0)
819    }
820    ///Bit 6 - Transmission complete interrupt enable
821    #[inline(always)]
822    pub fn tcie(&self) -> TCIE_R {
823        TCIE_R::new(((self.bits >> 6) & 1) != 0)
824    }
825    ///Bit 7 - TXE interrupt enable
826    #[inline(always)]
827    pub fn txeie(&self) -> TXEIE_R {
828        TXEIE_R::new(((self.bits >> 7) & 1) != 0)
829    }
830    ///Bit 8 - PE interrupt enable
831    #[inline(always)]
832    pub fn peie(&self) -> PEIE_R {
833        PEIE_R::new(((self.bits >> 8) & 1) != 0)
834    }
835    ///Bit 9 - Parity selection
836    #[inline(always)]
837    pub fn ps(&self) -> PS_R {
838        PS_R::new(((self.bits >> 9) & 1) != 0)
839    }
840    ///Bit 10 - Parity control enable
841    #[inline(always)]
842    pub fn pce(&self) -> PCE_R {
843        PCE_R::new(((self.bits >> 10) & 1) != 0)
844    }
845    ///Bit 11 - Wakeup method
846    #[inline(always)]
847    pub fn wake(&self) -> WAKE_R {
848        WAKE_R::new(((self.bits >> 11) & 1) != 0)
849    }
850    ///Bit 12 - Word length
851    #[inline(always)]
852    pub fn m(&self) -> M_R {
853        M_R::new(((self.bits >> 12) & 1) != 0)
854    }
855    ///Bit 13 - USART enable
856    #[inline(always)]
857    pub fn ue(&self) -> UE_R {
858        UE_R::new(((self.bits >> 13) & 1) != 0)
859    }
860}
861impl core::fmt::Debug for R {
862    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
863        f.debug_struct("CR1")
864            .field("ue", &self.ue())
865            .field("m", &self.m())
866            .field("wake", &self.wake())
867            .field("pce", &self.pce())
868            .field("ps", &self.ps())
869            .field("peie", &self.peie())
870            .field("txeie", &self.txeie())
871            .field("tcie", &self.tcie())
872            .field("rxneie", &self.rxneie())
873            .field("idleie", &self.idleie())
874            .field("te", &self.te())
875            .field("re", &self.re())
876            .field("rwu", &self.rwu())
877            .field("sbk", &self.sbk())
878            .finish()
879    }
880}
881impl W {
882    ///Bit 0 - Send break
883    #[inline(always)]
884    pub fn sbk(&mut self) -> SBK_W<CR1rs> {
885        SBK_W::new(self, 0)
886    }
887    ///Bit 1 - Receiver wakeup
888    #[inline(always)]
889    pub fn rwu(&mut self) -> RWU_W<CR1rs> {
890        RWU_W::new(self, 1)
891    }
892    ///Bit 2 - Receiver enable
893    #[inline(always)]
894    pub fn re(&mut self) -> RE_W<CR1rs> {
895        RE_W::new(self, 2)
896    }
897    ///Bit 3 - Transmitter enable
898    #[inline(always)]
899    pub fn te(&mut self) -> TE_W<CR1rs> {
900        TE_W::new(self, 3)
901    }
902    ///Bit 4 - IDLE interrupt enable
903    #[inline(always)]
904    pub fn idleie(&mut self) -> IDLEIE_W<CR1rs> {
905        IDLEIE_W::new(self, 4)
906    }
907    ///Bit 5 - RXNE interrupt enable
908    #[inline(always)]
909    pub fn rxneie(&mut self) -> RXNEIE_W<CR1rs> {
910        RXNEIE_W::new(self, 5)
911    }
912    ///Bit 6 - Transmission complete interrupt enable
913    #[inline(always)]
914    pub fn tcie(&mut self) -> TCIE_W<CR1rs> {
915        TCIE_W::new(self, 6)
916    }
917    ///Bit 7 - TXE interrupt enable
918    #[inline(always)]
919    pub fn txeie(&mut self) -> TXEIE_W<CR1rs> {
920        TXEIE_W::new(self, 7)
921    }
922    ///Bit 8 - PE interrupt enable
923    #[inline(always)]
924    pub fn peie(&mut self) -> PEIE_W<CR1rs> {
925        PEIE_W::new(self, 8)
926    }
927    ///Bit 9 - Parity selection
928    #[inline(always)]
929    pub fn ps(&mut self) -> PS_W<CR1rs> {
930        PS_W::new(self, 9)
931    }
932    ///Bit 10 - Parity control enable
933    #[inline(always)]
934    pub fn pce(&mut self) -> PCE_W<CR1rs> {
935        PCE_W::new(self, 10)
936    }
937    ///Bit 11 - Wakeup method
938    #[inline(always)]
939    pub fn wake(&mut self) -> WAKE_W<CR1rs> {
940        WAKE_W::new(self, 11)
941    }
942    ///Bit 12 - Word length
943    #[inline(always)]
944    pub fn m(&mut self) -> M_W<CR1rs> {
945        M_W::new(self, 12)
946    }
947    ///Bit 13 - USART enable
948    #[inline(always)]
949    pub fn ue(&mut self) -> UE_W<CR1rs> {
950        UE_W::new(self, 13)
951    }
952}
953/**Control register 1
954
955You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
956
957See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#USART1:CR1)*/
958pub struct CR1rs;
959impl crate::RegisterSpec for CR1rs {
960    type Ux = u16;
961}
962///`read()` method returns [`cr1::R`](R) reader structure
963impl crate::Readable for CR1rs {}
964///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
965impl crate::Writable for CR1rs {
966    type Safety = crate::Unsafe;
967}
968///`reset()` method sets CR1 to value 0
969impl crate::Resettable for CR1rs {}
stm32f1_staging/stm32f100/usart1/cr1.rs

stm32f1_staging/stm32f100/usart1/
cr1.rs
