stm32f1_staging/stm32f100/tim16/
dier.rs

1///Register `DIER` reader
2pub type R = crate::R<DIERrs>;
3///Register `DIER` writer
4pub type W = crate::W<DIERrs>;
5/**Update interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIE {
11    ///0: Update interrupt disabled
12    Disabled = 0,
13    ///1: Update interrupt enabled
14    Enabled = 1,
15}
16impl From<UIE> for bool {
17    #[inline(always)]
18    fn from(variant: UIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIE` reader - Update interrupt enable
23pub type UIE_R = crate::BitReader<UIE>;
24impl UIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIE {
28        match self.bits {
29            false => UIE::Disabled,
30            true => UIE::Enabled,
31        }
32    }
33    ///Update interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UIE::Disabled
37    }
38    ///Update interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UIE::Enabled
42    }
43}
44///Field `UIE` writer - Update interrupt enable
45pub type UIE_W<'a, REG> = crate::BitWriter<'a, REG, UIE>;
46impl<'a, REG> UIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Update interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UIE::Disabled)
54    }
55    ///Update interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UIE::Enabled)
59    }
60}
61/**Capture/Compare %s interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1IE {
67    ///0: CCx interrupt disabled
68    Disabled = 0,
69    ///1: CCx interrupt enabled
70    Enabled = 1,
71}
72impl From<CC1IE> for bool {
73    #[inline(always)]
74    fn from(variant: CC1IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCIE(1-1)` reader - Capture/Compare %s interrupt enable
79pub type CCIE_R = crate::BitReader<CC1IE>;
80impl CCIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1IE {
84        match self.bits {
85            false => CC1IE::Disabled,
86            true => CC1IE::Enabled,
87        }
88    }
89    ///CCx interrupt disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == CC1IE::Disabled
93    }
94    ///CCx interrupt enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == CC1IE::Enabled
98    }
99}
100///Field `CCIE(1-1)` writer - Capture/Compare %s interrupt enable
101pub type CCIE_W<'a, REG> = crate::BitWriter<'a, REG, CC1IE>;
102impl<'a, REG> CCIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///CCx interrupt disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1IE::Disabled)
110    }
111    ///CCx interrupt enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1IE::Enabled)
115    }
116}
117/**COM interrupt enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum COMIE {
123    ///0: COM interrupt disabled
124    Disabled = 0,
125    ///1: COM interrupt enabled
126    Enabled = 1,
127}
128impl From<COMIE> for bool {
129    #[inline(always)]
130    fn from(variant: COMIE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `COMIE` reader - COM interrupt enable
135pub type COMIE_R = crate::BitReader<COMIE>;
136impl COMIE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> COMIE {
140        match self.bits {
141            false => COMIE::Disabled,
142            true => COMIE::Enabled,
143        }
144    }
145    ///COM interrupt disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == COMIE::Disabled
149    }
150    ///COM interrupt enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == COMIE::Enabled
154    }
155}
156///Field `COMIE` writer - COM interrupt enable
157pub type COMIE_W<'a, REG> = crate::BitWriter<'a, REG, COMIE>;
158impl<'a, REG> COMIE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///COM interrupt disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(COMIE::Disabled)
166    }
167    ///COM interrupt enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(COMIE::Enabled)
171    }
172}
173///Field `TIE` reader - Trigger interrupt enable
174pub type TIE_R = crate::BitReader;
175///Field `TIE` writer - Trigger interrupt enable
176pub type TIE_W<'a, REG> = crate::BitWriter<'a, REG>;
177/**Break interrupt enable
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum BIE {
183    ///0: Break interrupt disabled
184    Disabled = 0,
185    ///1: Break interrupt enabled
186    Enabled = 1,
187}
188impl From<BIE> for bool {
189    #[inline(always)]
190    fn from(variant: BIE) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `BIE` reader - Break interrupt enable
195pub type BIE_R = crate::BitReader<BIE>;
196impl BIE_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> BIE {
200        match self.bits {
201            false => BIE::Disabled,
202            true => BIE::Enabled,
203        }
204    }
205    ///Break interrupt disabled
206    #[inline(always)]
207    pub fn is_disabled(&self) -> bool {
208        *self == BIE::Disabled
209    }
210    ///Break interrupt enabled
211    #[inline(always)]
212    pub fn is_enabled(&self) -> bool {
213        *self == BIE::Enabled
214    }
215}
216///Field `BIE` writer - Break interrupt enable
217pub type BIE_W<'a, REG> = crate::BitWriter<'a, REG, BIE>;
218impl<'a, REG> BIE_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///Break interrupt disabled
223    #[inline(always)]
224    pub fn disabled(self) -> &'a mut crate::W<REG> {
225        self.variant(BIE::Disabled)
226    }
227    ///Break interrupt enabled
228    #[inline(always)]
229    pub fn enabled(self) -> &'a mut crate::W<REG> {
230        self.variant(BIE::Enabled)
231    }
232}
233/**Update DMA request enable
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum UDE {
239    ///0: Update DMA request disabled
240    Disabled = 0,
241    ///1: Update DMA request enabled
242    Enabled = 1,
243}
244impl From<UDE> for bool {
245    #[inline(always)]
246    fn from(variant: UDE) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `UDE` reader - Update DMA request enable
251pub type UDE_R = crate::BitReader<UDE>;
252impl UDE_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> UDE {
256        match self.bits {
257            false => UDE::Disabled,
258            true => UDE::Enabled,
259        }
260    }
261    ///Update DMA request disabled
262    #[inline(always)]
263    pub fn is_disabled(&self) -> bool {
264        *self == UDE::Disabled
265    }
266    ///Update DMA request enabled
267    #[inline(always)]
268    pub fn is_enabled(&self) -> bool {
269        *self == UDE::Enabled
270    }
271}
272///Field `UDE` writer - Update DMA request enable
273pub type UDE_W<'a, REG> = crate::BitWriter<'a, REG, UDE>;
274impl<'a, REG> UDE_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Update DMA request disabled
279    #[inline(always)]
280    pub fn disabled(self) -> &'a mut crate::W<REG> {
281        self.variant(UDE::Disabled)
282    }
283    ///Update DMA request enabled
284    #[inline(always)]
285    pub fn enabled(self) -> &'a mut crate::W<REG> {
286        self.variant(UDE::Enabled)
287    }
288}
289/**Capture/Compare %s DMA request enable
290
291Value on reset: 0*/
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum CC1DE {
295    ///0: CCx DMA request disabled
296    Disabled = 0,
297    ///1: CCx DMA request enabled
298    Enabled = 1,
299}
300impl From<CC1DE> for bool {
301    #[inline(always)]
302    fn from(variant: CC1DE) -> Self {
303        variant as u8 != 0
304    }
305}
306///Field `CCDE(1-1)` reader - Capture/Compare %s DMA request enable
307pub type CCDE_R = crate::BitReader<CC1DE>;
308impl CCDE_R {
309    ///Get enumerated values variant
310    #[inline(always)]
311    pub const fn variant(&self) -> CC1DE {
312        match self.bits {
313            false => CC1DE::Disabled,
314            true => CC1DE::Enabled,
315        }
316    }
317    ///CCx DMA request disabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == CC1DE::Disabled
321    }
322    ///CCx DMA request enabled
323    #[inline(always)]
324    pub fn is_enabled(&self) -> bool {
325        *self == CC1DE::Enabled
326    }
327}
328///Field `CCDE(1-1)` writer - Capture/Compare %s DMA request enable
329pub type CCDE_W<'a, REG> = crate::BitWriter<'a, REG, CC1DE>;
330impl<'a, REG> CCDE_W<'a, REG>
331where
332    REG: crate::Writable + crate::RegisterSpec,
333{
334    ///CCx DMA request disabled
335    #[inline(always)]
336    pub fn disabled(self) -> &'a mut crate::W<REG> {
337        self.variant(CC1DE::Disabled)
338    }
339    ///CCx DMA request enabled
340    #[inline(always)]
341    pub fn enabled(self) -> &'a mut crate::W<REG> {
342        self.variant(CC1DE::Enabled)
343    }
344}
345///Field `TDE` reader - Trigger DMA request enable
346pub type TDE_R = crate::BitReader;
347///Field `TDE` writer - Trigger DMA request enable
348pub type TDE_W<'a, REG> = crate::BitWriter<'a, REG>;
349impl R {
350    ///Bit 0 - Update interrupt enable
351    #[inline(always)]
352    pub fn uie(&self) -> UIE_R {
353        UIE_R::new((self.bits & 1) != 0)
354    }
355    ///Capture/Compare (1-1) interrupt enable
356    ///
357    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
358    #[inline(always)]
359    pub fn ccie(&self, n: u8) -> CCIE_R {
360        #[allow(clippy::no_effect)] [(); 1][n as usize];
361        CCIE_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
362    }
363    ///Iterator for array of:
364    ///Capture/Compare (1-1) interrupt enable
365    #[inline(always)]
366    pub fn ccie_iter(&self) -> impl Iterator<Item = CCIE_R> + '_ {
367        (0..1).map(move |n| CCIE_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
368    }
369    ///Bit 1 - Capture/Compare 1 interrupt enable
370    #[inline(always)]
371    pub fn cc1ie(&self) -> CCIE_R {
372        CCIE_R::new(((self.bits >> 1) & 1) != 0)
373    }
374    ///Bit 5 - COM interrupt enable
375    #[inline(always)]
376    pub fn comie(&self) -> COMIE_R {
377        COMIE_R::new(((self.bits >> 5) & 1) != 0)
378    }
379    ///Bit 6 - Trigger interrupt enable
380    #[inline(always)]
381    pub fn tie(&self) -> TIE_R {
382        TIE_R::new(((self.bits >> 6) & 1) != 0)
383    }
384    ///Bit 7 - Break interrupt enable
385    #[inline(always)]
386    pub fn bie(&self) -> BIE_R {
387        BIE_R::new(((self.bits >> 7) & 1) != 0)
388    }
389    ///Bit 8 - Update DMA request enable
390    #[inline(always)]
391    pub fn ude(&self) -> UDE_R {
392        UDE_R::new(((self.bits >> 8) & 1) != 0)
393    }
394    ///Capture/Compare (1-1) DMA request enable
395    ///
396    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1DE` field.</div>
397    #[inline(always)]
398    pub fn ccde(&self, n: u8) -> CCDE_R {
399        #[allow(clippy::no_effect)] [(); 1][n as usize];
400        CCDE_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0)
401    }
402    ///Iterator for array of:
403    ///Capture/Compare (1-1) DMA request enable
404    #[inline(always)]
405    pub fn ccde_iter(&self) -> impl Iterator<Item = CCDE_R> + '_ {
406        (0..1).map(move |n| CCDE_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0))
407    }
408    ///Bit 9 - Capture/Compare 1 DMA request enable
409    #[inline(always)]
410    pub fn cc1de(&self) -> CCDE_R {
411        CCDE_R::new(((self.bits >> 9) & 1) != 0)
412    }
413    ///Bit 14 - Trigger DMA request enable
414    #[inline(always)]
415    pub fn tde(&self) -> TDE_R {
416        TDE_R::new(((self.bits >> 14) & 1) != 0)
417    }
418}
419impl core::fmt::Debug for R {
420    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
421        f.debug_struct("DIER")
422            .field("tde", &self.tde())
423            .field("cc1de", &self.cc1de())
424            .field("ude", &self.ude())
425            .field("bie", &self.bie())
426            .field("tie", &self.tie())
427            .field("comie", &self.comie())
428            .field("cc1ie", &self.cc1ie())
429            .field("uie", &self.uie())
430            .finish()
431    }
432}
433impl W {
434    ///Bit 0 - Update interrupt enable
435    #[inline(always)]
436    pub fn uie(&mut self) -> UIE_W<DIERrs> {
437        UIE_W::new(self, 0)
438    }
439    ///Capture/Compare (1-1) interrupt enable
440    ///
441    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
442    #[inline(always)]
443    pub fn ccie(&mut self, n: u8) -> CCIE_W<DIERrs> {
444        #[allow(clippy::no_effect)] [(); 1][n as usize];
445        CCIE_W::new(self, n * 0 + 1)
446    }
447    ///Bit 1 - Capture/Compare 1 interrupt enable
448    #[inline(always)]
449    pub fn cc1ie(&mut self) -> CCIE_W<DIERrs> {
450        CCIE_W::new(self, 1)
451    }
452    ///Bit 5 - COM interrupt enable
453    #[inline(always)]
454    pub fn comie(&mut self) -> COMIE_W<DIERrs> {
455        COMIE_W::new(self, 5)
456    }
457    ///Bit 6 - Trigger interrupt enable
458    #[inline(always)]
459    pub fn tie(&mut self) -> TIE_W<DIERrs> {
460        TIE_W::new(self, 6)
461    }
462    ///Bit 7 - Break interrupt enable
463    #[inline(always)]
464    pub fn bie(&mut self) -> BIE_W<DIERrs> {
465        BIE_W::new(self, 7)
466    }
467    ///Bit 8 - Update DMA request enable
468    #[inline(always)]
469    pub fn ude(&mut self) -> UDE_W<DIERrs> {
470        UDE_W::new(self, 8)
471    }
472    ///Capture/Compare (1-1) DMA request enable
473    ///
474    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1DE` field.</div>
475    #[inline(always)]
476    pub fn ccde(&mut self, n: u8) -> CCDE_W<DIERrs> {
477        #[allow(clippy::no_effect)] [(); 1][n as usize];
478        CCDE_W::new(self, n * 0 + 9)
479    }
480    ///Bit 9 - Capture/Compare 1 DMA request enable
481    #[inline(always)]
482    pub fn cc1de(&mut self) -> CCDE_W<DIERrs> {
483        CCDE_W::new(self, 9)
484    }
485    ///Bit 14 - Trigger DMA request enable
486    #[inline(always)]
487    pub fn tde(&mut self) -> TDE_W<DIERrs> {
488        TDE_W::new(self, 14)
489    }
490}
491/**DMA/Interrupt enable register
492
493You can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
494
495See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16:DIER)*/
496pub struct DIERrs;
497impl crate::RegisterSpec for DIERrs {
498    type Ux = u32;
499}
500///`read()` method returns [`dier::R`](R) reader structure
501impl crate::Readable for DIERrs {}
502///`write(|w| ..)` method takes [`dier::W`](W) writer structure
503impl crate::Writable for DIERrs {
504    type Safety = crate::Unsafe;
505}
506///`reset()` method sets DIER to value 0
507impl crate::Resettable for DIERrs {}
stm32f1_staging/stm32f100/tim16/dier.rs

stm32f1_staging/stm32f100/tim16/
dier.rs
