stm32f1_staging/stm32f100/tim16/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Capture/compare preloaded control
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CCPC {
11    ///0: CCxE, CCxNE and OCxM bits are not preloaded
12    NotPreloaded = 0,
13    ///1: CCxE, CCxNE and OCxM bits are preloaded
14    Preloaded = 1,
15}
16impl From<CCPC> for bool {
17    #[inline(always)]
18    fn from(variant: CCPC) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCPC` reader - Capture/compare preloaded control
23pub type CCPC_R = crate::BitReader<CCPC>;
24impl CCPC_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CCPC {
28        match self.bits {
29            false => CCPC::NotPreloaded,
30            true => CCPC::Preloaded,
31        }
32    }
33    ///CCxE, CCxNE and OCxM bits are not preloaded
34    #[inline(always)]
35    pub fn is_not_preloaded(&self) -> bool {
36        *self == CCPC::NotPreloaded
37    }
38    ///CCxE, CCxNE and OCxM bits are preloaded
39    #[inline(always)]
40    pub fn is_preloaded(&self) -> bool {
41        *self == CCPC::Preloaded
42    }
43}
44///Field `CCPC` writer - Capture/compare preloaded control
45pub type CCPC_W<'a, REG> = crate::BitWriter<'a, REG, CCPC>;
46impl<'a, REG> CCPC_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///CCxE, CCxNE and OCxM bits are not preloaded
51    #[inline(always)]
52    pub fn not_preloaded(self) -> &'a mut crate::W<REG> {
53        self.variant(CCPC::NotPreloaded)
54    }
55    ///CCxE, CCxNE and OCxM bits are preloaded
56    #[inline(always)]
57    pub fn preloaded(self) -> &'a mut crate::W<REG> {
58        self.variant(CCPC::Preloaded)
59    }
60}
61/**Capture/compare control update selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CCUS {
67    ///0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
68    Sw = 0,
69    ///1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
70    SwOrEdge = 1,
71}
72impl From<CCUS> for bool {
73    #[inline(always)]
74    fn from(variant: CCUS) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCUS` reader - Capture/compare control update selection
79pub type CCUS_R = crate::BitReader<CCUS>;
80impl CCUS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CCUS {
84        match self.bits {
85            false => CCUS::Sw,
86            true => CCUS::SwOrEdge,
87        }
88    }
89    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
90    #[inline(always)]
91    pub fn is_sw(&self) -> bool {
92        *self == CCUS::Sw
93    }
94    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
95    #[inline(always)]
96    pub fn is_sw_or_edge(&self) -> bool {
97        *self == CCUS::SwOrEdge
98    }
99}
100///Field `CCUS` writer - Capture/compare control update selection
101pub type CCUS_W<'a, REG> = crate::BitWriter<'a, REG, CCUS>;
102impl<'a, REG> CCUS_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
107    #[inline(always)]
108    pub fn sw(self) -> &'a mut crate::W<REG> {
109        self.variant(CCUS::Sw)
110    }
111    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
112    #[inline(always)]
113    pub fn sw_or_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CCUS::SwOrEdge)
115    }
116}
117/**Capture/compare DMA selection
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CCDS {
123    ///0: CCx DMA request sent when CCx event occurs
124    OnCompare = 0,
125    ///1: CCx DMA request sent when update event occurs
126    OnUpdate = 1,
127}
128impl From<CCDS> for bool {
129    #[inline(always)]
130    fn from(variant: CCDS) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCDS` reader - Capture/compare DMA selection
135pub type CCDS_R = crate::BitReader<CCDS>;
136impl CCDS_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CCDS {
140        match self.bits {
141            false => CCDS::OnCompare,
142            true => CCDS::OnUpdate,
143        }
144    }
145    ///CCx DMA request sent when CCx event occurs
146    #[inline(always)]
147    pub fn is_on_compare(&self) -> bool {
148        *self == CCDS::OnCompare
149    }
150    ///CCx DMA request sent when update event occurs
151    #[inline(always)]
152    pub fn is_on_update(&self) -> bool {
153        *self == CCDS::OnUpdate
154    }
155}
156///Field `CCDS` writer - Capture/compare DMA selection
157pub type CCDS_W<'a, REG> = crate::BitWriter<'a, REG, CCDS>;
158impl<'a, REG> CCDS_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///CCx DMA request sent when CCx event occurs
163    #[inline(always)]
164    pub fn on_compare(self) -> &'a mut crate::W<REG> {
165        self.variant(CCDS::OnCompare)
166    }
167    ///CCx DMA request sent when update event occurs
168    #[inline(always)]
169    pub fn on_update(self) -> &'a mut crate::W<REG> {
170        self.variant(CCDS::OnUpdate)
171    }
172}
173/**Output Idle state (OC%s output)
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum OIS1 {
179    ///0: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
180    Reset = 0,
181    ///1: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
182    Set = 1,
183}
184impl From<OIS1> for bool {
185    #[inline(always)]
186    fn from(variant: OIS1) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `OIS(1-1)` reader - Output Idle state (OC%s output)
191pub type OIS_R = crate::BitReader<OIS1>;
192impl OIS_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> OIS1 {
196        match self.bits {
197            false => OIS1::Reset,
198            true => OIS1::Set,
199        }
200    }
201    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
202    #[inline(always)]
203    pub fn is_reset(&self) -> bool {
204        *self == OIS1::Reset
205    }
206    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
207    #[inline(always)]
208    pub fn is_set(&self) -> bool {
209        *self == OIS1::Set
210    }
211}
212///Field `OIS(1-1)` writer - Output Idle state (OC%s output)
213pub type OIS_W<'a, REG> = crate::BitWriter<'a, REG, OIS1>;
214impl<'a, REG> OIS_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
219    #[inline(always)]
220    pub fn reset(self) -> &'a mut crate::W<REG> {
221        self.variant(OIS1::Reset)
222    }
223    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
224    #[inline(always)]
225    pub fn set_(self) -> &'a mut crate::W<REG> {
226        self.variant(OIS1::Set)
227    }
228}
229/**Output Idle state (OC%sN output)
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum OIS1N {
235    ///0: OCxN=0 after a dead-time when MOE=0
236    Reset = 0,
237    ///1: OCxN=1 after a dead-time when MOE=0
238    Set = 1,
239}
240impl From<OIS1N> for bool {
241    #[inline(always)]
242    fn from(variant: OIS1N) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `OISN(1-1)` reader - Output Idle state (OC%sN output)
247pub type OISN_R = crate::BitReader<OIS1N>;
248impl OISN_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> OIS1N {
252        match self.bits {
253            false => OIS1N::Reset,
254            true => OIS1N::Set,
255        }
256    }
257    ///OCxN=0 after a dead-time when MOE=0
258    #[inline(always)]
259    pub fn is_reset(&self) -> bool {
260        *self == OIS1N::Reset
261    }
262    ///OCxN=1 after a dead-time when MOE=0
263    #[inline(always)]
264    pub fn is_set(&self) -> bool {
265        *self == OIS1N::Set
266    }
267}
268///Field `OISN(1-1)` writer - Output Idle state (OC%sN output)
269pub type OISN_W<'a, REG> = crate::BitWriter<'a, REG, OIS1N>;
270impl<'a, REG> OISN_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///OCxN=0 after a dead-time when MOE=0
275    #[inline(always)]
276    pub fn reset(self) -> &'a mut crate::W<REG> {
277        self.variant(OIS1N::Reset)
278    }
279    ///OCxN=1 after a dead-time when MOE=0
280    #[inline(always)]
281    pub fn set_(self) -> &'a mut crate::W<REG> {
282        self.variant(OIS1N::Set)
283    }
284}
285impl R {
286    ///Bit 0 - Capture/compare preloaded control
287    #[inline(always)]
288    pub fn ccpc(&self) -> CCPC_R {
289        CCPC_R::new((self.bits & 1) != 0)
290    }
291    ///Bit 2 - Capture/compare control update selection
292    #[inline(always)]
293    pub fn ccus(&self) -> CCUS_R {
294        CCUS_R::new(((self.bits >> 2) & 1) != 0)
295    }
296    ///Bit 3 - Capture/compare DMA selection
297    #[inline(always)]
298    pub fn ccds(&self) -> CCDS_R {
299        CCDS_R::new(((self.bits >> 3) & 1) != 0)
300    }
301    ///Output Idle state (OC(1-1) output)
302    ///
303    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
304    #[inline(always)]
305    pub fn ois(&self, n: u8) -> OIS_R {
306        #[allow(clippy::no_effect)] [(); 1][n as usize];
307        OIS_R::new(((self.bits >> (n * 0 + 8)) & 1) != 0)
308    }
309    ///Iterator for array of:
310    ///Output Idle state (OC(1-1) output)
311    #[inline(always)]
312    pub fn ois_iter(&self) -> impl Iterator<Item = OIS_R> + '_ {
313        (0..1).map(move |n| OIS_R::new(((self.bits >> (n * 0 + 8)) & 1) != 0))
314    }
315    ///Bit 8 - Output Idle state (OC1 output)
316    #[inline(always)]
317    pub fn ois1(&self) -> OIS_R {
318        OIS_R::new(((self.bits >> 8) & 1) != 0)
319    }
320    ///Output Idle state (OC(1-1)N output)
321    ///
322    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
323    #[inline(always)]
324    pub fn oisn(&self, n: u8) -> OISN_R {
325        #[allow(clippy::no_effect)] [(); 1][n as usize];
326        OISN_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0)
327    }
328    ///Iterator for array of:
329    ///Output Idle state (OC(1-1)N output)
330    #[inline(always)]
331    pub fn oisn_iter(&self) -> impl Iterator<Item = OISN_R> + '_ {
332        (0..1).map(move |n| OISN_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0))
333    }
334    ///Bit 9 - Output Idle state (OC1N output)
335    #[inline(always)]
336    pub fn ois1n(&self) -> OISN_R {
337        OISN_R::new(((self.bits >> 9) & 1) != 0)
338    }
339}
340impl core::fmt::Debug for R {
341    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
342        f.debug_struct("CR2")
343            .field("ois1n", &self.ois1n())
344            .field("ois1", &self.ois1())
345            .field("ccds", &self.ccds())
346            .field("ccus", &self.ccus())
347            .field("ccpc", &self.ccpc())
348            .finish()
349    }
350}
351impl W {
352    ///Bit 0 - Capture/compare preloaded control
353    #[inline(always)]
354    pub fn ccpc(&mut self) -> CCPC_W<CR2rs> {
355        CCPC_W::new(self, 0)
356    }
357    ///Bit 2 - Capture/compare control update selection
358    #[inline(always)]
359    pub fn ccus(&mut self) -> CCUS_W<CR2rs> {
360        CCUS_W::new(self, 2)
361    }
362    ///Bit 3 - Capture/compare DMA selection
363    #[inline(always)]
364    pub fn ccds(&mut self) -> CCDS_W<CR2rs> {
365        CCDS_W::new(self, 3)
366    }
367    ///Output Idle state (OC(1-1) output)
368    ///
369    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
370    #[inline(always)]
371    pub fn ois(&mut self, n: u8) -> OIS_W<CR2rs> {
372        #[allow(clippy::no_effect)] [(); 1][n as usize];
373        OIS_W::new(self, n * 0 + 8)
374    }
375    ///Bit 8 - Output Idle state (OC1 output)
376    #[inline(always)]
377    pub fn ois1(&mut self) -> OIS_W<CR2rs> {
378        OIS_W::new(self, 8)
379    }
380    ///Output Idle state (OC(1-1)N output)
381    ///
382    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
383    #[inline(always)]
384    pub fn oisn(&mut self, n: u8) -> OISN_W<CR2rs> {
385        #[allow(clippy::no_effect)] [(); 1][n as usize];
386        OISN_W::new(self, n * 0 + 9)
387    }
388    ///Bit 9 - Output Idle state (OC1N output)
389    #[inline(always)]
390    pub fn ois1n(&mut self) -> OISN_W<CR2rs> {
391        OISN_W::new(self, 9)
392    }
393}
394/**control register 2
395
396You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
397
398See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16:CR2)*/
399pub struct CR2rs;
400impl crate::RegisterSpec for CR2rs {
401    type Ux = u32;
402}
403///`read()` method returns [`cr2::R`](R) reader structure
404impl crate::Readable for CR2rs {}
405///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
406impl crate::Writable for CR2rs {
407    type Safety = crate::Unsafe;
408}
409///`reset()` method sets CR2 to value 0
410impl crate::Resettable for CR2rs {}
stm32f1_staging/stm32f100/tim16/cr2.rs

stm32f1_staging/stm32f100/tim16/
cr2.rs
