stm32f1_staging/stm32f100/tim16/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-1)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-1)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-1)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-1)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117/**Capture/Compare %s complementary output enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CC1NE {
123    ///0: Complementary output disabled
124    Disabled = 0,
125    ///1: Complementary output enabled
126    Enabled = 1,
127}
128impl From<CC1NE> for bool {
129    #[inline(always)]
130    fn from(variant: CC1NE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCNE(1-1)` reader - Capture/Compare %s complementary output enable
135pub type CCNE_R = crate::BitReader<CC1NE>;
136impl CCNE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CC1NE {
140        match self.bits {
141            false => CC1NE::Disabled,
142            true => CC1NE::Enabled,
143        }
144    }
145    ///Complementary output disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == CC1NE::Disabled
149    }
150    ///Complementary output enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == CC1NE::Enabled
154    }
155}
156///Field `CCNE(1-1)` writer - Capture/Compare %s complementary output enable
157pub type CCNE_W<'a, REG> = crate::BitWriter<'a, REG, CC1NE>;
158impl<'a, REG> CCNE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Complementary output disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(CC1NE::Disabled)
166    }
167    ///Complementary output enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(CC1NE::Enabled)
171    }
172}
173/**Capture/Compare %s output Polarity
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum CC1NP {
179    ///0: OCxN active high
180    ActiveHigh = 0,
181    ///1: OCxN active low
182    ActiveLow = 1,
183}
184impl From<CC1NP> for bool {
185    #[inline(always)]
186    fn from(variant: CC1NP) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `CCNP(1-1)` reader - Capture/Compare %s output Polarity
191pub type CCNP_R = crate::BitReader<CC1NP>;
192impl CCNP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> CC1NP {
196        match self.bits {
197            false => CC1NP::ActiveHigh,
198            true => CC1NP::ActiveLow,
199        }
200    }
201    ///OCxN active high
202    #[inline(always)]
203    pub fn is_active_high(&self) -> bool {
204        *self == CC1NP::ActiveHigh
205    }
206    ///OCxN active low
207    #[inline(always)]
208    pub fn is_active_low(&self) -> bool {
209        *self == CC1NP::ActiveLow
210    }
211}
212///Field `CCNP(1-1)` writer - Capture/Compare %s output Polarity
213pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG, CC1NP>;
214impl<'a, REG> CCNP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///OCxN active high
219    #[inline(always)]
220    pub fn active_high(self) -> &'a mut crate::W<REG> {
221        self.variant(CC1NP::ActiveHigh)
222    }
223    ///OCxN active low
224    #[inline(always)]
225    pub fn active_low(self) -> &'a mut crate::W<REG> {
226        self.variant(CC1NP::ActiveLow)
227    }
228}
229impl R {
230    ///Capture/Compare (1-1) output enable
231    ///
232    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
233    #[inline(always)]
234    pub fn cce(&self, n: u8) -> CCE_R {
235        #[allow(clippy::no_effect)] [(); 1][n as usize];
236        CCE_R::new(((self.bits >> (n * 0)) & 1) != 0)
237    }
238    ///Iterator for array of:
239    ///Capture/Compare (1-1) output enable
240    #[inline(always)]
241    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
242        (0..1).map(move |n| CCE_R::new(((self.bits >> (n * 0)) & 1) != 0))
243    }
244    ///Bit 0 - Capture/Compare 1 output enable
245    #[inline(always)]
246    pub fn cc1e(&self) -> CCE_R {
247        CCE_R::new((self.bits & 1) != 0)
248    }
249    ///Capture/Compare (1-1) output Polarity
250    ///
251    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
252    #[inline(always)]
253    pub fn ccp(&self, n: u8) -> CCP_R {
254        #[allow(clippy::no_effect)] [(); 1][n as usize];
255        CCP_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
256    }
257    ///Iterator for array of:
258    ///Capture/Compare (1-1) output Polarity
259    #[inline(always)]
260    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
261        (0..1).map(move |n| CCP_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
262    }
263    ///Bit 1 - Capture/Compare 1 output Polarity
264    #[inline(always)]
265    pub fn cc1p(&self) -> CCP_R {
266        CCP_R::new(((self.bits >> 1) & 1) != 0)
267    }
268    ///Capture/Compare (1-1) complementary output enable
269    ///
270    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
271    #[inline(always)]
272    pub fn ccne(&self, n: u8) -> CCNE_R {
273        #[allow(clippy::no_effect)] [(); 1][n as usize];
274        CCNE_R::new(((self.bits >> (n * 0 + 2)) & 1) != 0)
275    }
276    ///Iterator for array of:
277    ///Capture/Compare (1-1) complementary output enable
278    #[inline(always)]
279    pub fn ccne_iter(&self) -> impl Iterator<Item = CCNE_R> + '_ {
280        (0..1).map(move |n| CCNE_R::new(((self.bits >> (n * 0 + 2)) & 1) != 0))
281    }
282    ///Bit 2 - Capture/Compare 1 complementary output enable
283    #[inline(always)]
284    pub fn cc1ne(&self) -> CCNE_R {
285        CCNE_R::new(((self.bits >> 2) & 1) != 0)
286    }
287    ///Capture/Compare (1-1) output Polarity
288    ///
289    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
290    #[inline(always)]
291    pub fn ccnp(&self, n: u8) -> CCNP_R {
292        #[allow(clippy::no_effect)] [(); 1][n as usize];
293        CCNP_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0)
294    }
295    ///Iterator for array of:
296    ///Capture/Compare (1-1) output Polarity
297    #[inline(always)]
298    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
299        (0..1).map(move |n| CCNP_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0))
300    }
301    ///Bit 3 - Capture/Compare 1 output Polarity
302    #[inline(always)]
303    pub fn cc1np(&self) -> CCNP_R {
304        CCNP_R::new(((self.bits >> 3) & 1) != 0)
305    }
306}
307impl core::fmt::Debug for R {
308    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
309        f.debug_struct("CCER")
310            .field("cc1np", &self.cc1np())
311            .field("cc1ne", &self.cc1ne())
312            .field("cc1p", &self.cc1p())
313            .field("cc1e", &self.cc1e())
314            .finish()
315    }
316}
317impl W {
318    ///Capture/Compare (1-1) output enable
319    ///
320    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
321    #[inline(always)]
322    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
323        #[allow(clippy::no_effect)] [(); 1][n as usize];
324        CCE_W::new(self, n * 0)
325    }
326    ///Bit 0 - Capture/Compare 1 output enable
327    #[inline(always)]
328    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
329        CCE_W::new(self, 0)
330    }
331    ///Capture/Compare (1-1) output Polarity
332    ///
333    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
334    #[inline(always)]
335    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
336        #[allow(clippy::no_effect)] [(); 1][n as usize];
337        CCP_W::new(self, n * 0 + 1)
338    }
339    ///Bit 1 - Capture/Compare 1 output Polarity
340    #[inline(always)]
341    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
342        CCP_W::new(self, 1)
343    }
344    ///Capture/Compare (1-1) complementary output enable
345    ///
346    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
347    #[inline(always)]
348    pub fn ccne(&mut self, n: u8) -> CCNE_W<CCERrs> {
349        #[allow(clippy::no_effect)] [(); 1][n as usize];
350        CCNE_W::new(self, n * 0 + 2)
351    }
352    ///Bit 2 - Capture/Compare 1 complementary output enable
353    #[inline(always)]
354    pub fn cc1ne(&mut self) -> CCNE_W<CCERrs> {
355        CCNE_W::new(self, 2)
356    }
357    ///Capture/Compare (1-1) output Polarity
358    ///
359    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
360    #[inline(always)]
361    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
362        #[allow(clippy::no_effect)] [(); 1][n as usize];
363        CCNP_W::new(self, n * 0 + 3)
364    }
365    ///Bit 3 - Capture/Compare 1 output Polarity
366    #[inline(always)]
367    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
368        CCNP_W::new(self, 3)
369    }
370}
371/**capture/compare enable register
372
373You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
374
375See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16:CCER)*/
376pub struct CCERrs;
377impl crate::RegisterSpec for CCERrs {
378    type Ux = u32;
379}
380///`read()` method returns [`ccer::R`](R) reader structure
381impl crate::Readable for CCERrs {}
382///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
383impl crate::Writable for CCERrs {
384    type Safety = crate::Unsafe;
385}
386///`reset()` method sets CCER to value 0
387impl crate::Resettable for CCERrs {}
stm32f1_staging/stm32f100/tim16/ccer.rs

stm32f1_staging/stm32f100/tim16/
ccer.rs
