stm32f1_staging/stm32f100/tim16/
bdtr.rs

1///Register `BDTR` reader
2pub type R = crate::R<BDTRrs>;
3///Register `BDTR` writer
4pub type W = crate::W<BDTRrs>;
5///Field `DTG` reader - Dead-time generator setup
6pub type DTG_R = crate::FieldReader;
7///Field `DTG` writer - Dead-time generator setup
8pub type DTG_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9///Field `LOCK` reader - Lock configuration
10pub type LOCK_R = crate::FieldReader;
11///Field `LOCK` writer - Lock configuration
12pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `OSSI` reader - Off-state selection for Idle mode
14pub type OSSI_R = crate::BitReader;
15///Field `OSSI` writer - Off-state selection for Idle mode
16pub type OSSI_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `OSSR` reader - Off-state selection for Run mode
18pub type OSSR_R = crate::BitReader;
19///Field `OSSR` writer - Off-state selection for Run mode
20pub type OSSR_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `BKE` reader - Break enable
22pub type BKE_R = crate::BitReader;
23///Field `BKE` writer - Break enable
24pub type BKE_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `BKP` reader - Break polarity
26pub type BKP_R = crate::BitReader;
27///Field `BKP` writer - Break polarity
28pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `AOE` reader - Automatic output enable
30pub type AOE_R = crate::BitReader;
31///Field `AOE` writer - Automatic output enable
32pub type AOE_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `MOE` reader - Main output enable
34pub type MOE_R = crate::BitReader;
35///Field `MOE` writer - Main output enable
36pub type MOE_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    ///Bits 0:7 - Dead-time generator setup
39    #[inline(always)]
40    pub fn dtg(&self) -> DTG_R {
41        DTG_R::new((self.bits & 0xff) as u8)
42    }
43    ///Bits 8:9 - Lock configuration
44    #[inline(always)]
45    pub fn lock(&self) -> LOCK_R {
46        LOCK_R::new(((self.bits >> 8) & 3) as u8)
47    }
48    ///Bit 10 - Off-state selection for Idle mode
49    #[inline(always)]
50    pub fn ossi(&self) -> OSSI_R {
51        OSSI_R::new(((self.bits >> 10) & 1) != 0)
52    }
53    ///Bit 11 - Off-state selection for Run mode
54    #[inline(always)]
55    pub fn ossr(&self) -> OSSR_R {
56        OSSR_R::new(((self.bits >> 11) & 1) != 0)
57    }
58    ///Bit 12 - Break enable
59    #[inline(always)]
60    pub fn bke(&self) -> BKE_R {
61        BKE_R::new(((self.bits >> 12) & 1) != 0)
62    }
63    ///Bit 13 - Break polarity
64    #[inline(always)]
65    pub fn bkp(&self) -> BKP_R {
66        BKP_R::new(((self.bits >> 13) & 1) != 0)
67    }
68    ///Bit 14 - Automatic output enable
69    #[inline(always)]
70    pub fn aoe(&self) -> AOE_R {
71        AOE_R::new(((self.bits >> 14) & 1) != 0)
72    }
73    ///Bit 15 - Main output enable
74    #[inline(always)]
75    pub fn moe(&self) -> MOE_R {
76        MOE_R::new(((self.bits >> 15) & 1) != 0)
77    }
78}
79impl core::fmt::Debug for R {
80    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
81        f.debug_struct("BDTR")
82            .field("moe", &self.moe())
83            .field("aoe", &self.aoe())
84            .field("bkp", &self.bkp())
85            .field("bke", &self.bke())
86            .field("ossr", &self.ossr())
87            .field("ossi", &self.ossi())
88            .field("lock", &self.lock())
89            .field("dtg", &self.dtg())
90            .finish()
91    }
92}
93impl W {
94    ///Bits 0:7 - Dead-time generator setup
95    #[inline(always)]
96    pub fn dtg(&mut self) -> DTG_W<BDTRrs> {
97        DTG_W::new(self, 0)
98    }
99    ///Bits 8:9 - Lock configuration
100    #[inline(always)]
101    pub fn lock(&mut self) -> LOCK_W<BDTRrs> {
102        LOCK_W::new(self, 8)
103    }
104    ///Bit 10 - Off-state selection for Idle mode
105    #[inline(always)]
106    pub fn ossi(&mut self) -> OSSI_W<BDTRrs> {
107        OSSI_W::new(self, 10)
108    }
109    ///Bit 11 - Off-state selection for Run mode
110    #[inline(always)]
111    pub fn ossr(&mut self) -> OSSR_W<BDTRrs> {
112        OSSR_W::new(self, 11)
113    }
114    ///Bit 12 - Break enable
115    #[inline(always)]
116    pub fn bke(&mut self) -> BKE_W<BDTRrs> {
117        BKE_W::new(self, 12)
118    }
119    ///Bit 13 - Break polarity
120    #[inline(always)]
121    pub fn bkp(&mut self) -> BKP_W<BDTRrs> {
122        BKP_W::new(self, 13)
123    }
124    ///Bit 14 - Automatic output enable
125    #[inline(always)]
126    pub fn aoe(&mut self) -> AOE_W<BDTRrs> {
127        AOE_W::new(self, 14)
128    }
129    ///Bit 15 - Main output enable
130    #[inline(always)]
131    pub fn moe(&mut self) -> MOE_W<BDTRrs> {
132        MOE_W::new(self, 15)
133    }
134}
135/**break and dead-time register
136
137You can [`read`](crate::Reg::read) this register and get [`bdtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16:BDTR)*/
140pub struct BDTRrs;
141impl crate::RegisterSpec for BDTRrs {
142    type Ux = u32;
143}
144///`read()` method returns [`bdtr::R`](R) reader structure
145impl crate::Readable for BDTRrs {}
146///`write(|w| ..)` method takes [`bdtr::W`](W) writer structure
147impl crate::Writable for BDTRrs {
148    type Safety = crate::Unsafe;
149}
150///`reset()` method sets BDTR to value 0
151impl crate::Resettable for BDTRrs {}
stm32f1_staging/stm32f100/tim16/bdtr.rs

stm32f1_staging/stm32f100/tim16/
bdtr.rs
