stm32f1_staging/stm32f100/tim15/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Capture/compare preloaded control
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CCPC {
11    ///0: CCxE, CCxNE and OCxM bits are not preloaded
12    NotPreloaded = 0,
13    ///1: CCxE, CCxNE and OCxM bits are preloaded
14    Preloaded = 1,
15}
16impl From<CCPC> for bool {
17    #[inline(always)]
18    fn from(variant: CCPC) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCPC` reader - Capture/compare preloaded control
23pub type CCPC_R = crate::BitReader<CCPC>;
24impl CCPC_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CCPC {
28        match self.bits {
29            false => CCPC::NotPreloaded,
30            true => CCPC::Preloaded,
31        }
32    }
33    ///CCxE, CCxNE and OCxM bits are not preloaded
34    #[inline(always)]
35    pub fn is_not_preloaded(&self) -> bool {
36        *self == CCPC::NotPreloaded
37    }
38    ///CCxE, CCxNE and OCxM bits are preloaded
39    #[inline(always)]
40    pub fn is_preloaded(&self) -> bool {
41        *self == CCPC::Preloaded
42    }
43}
44///Field `CCPC` writer - Capture/compare preloaded control
45pub type CCPC_W<'a, REG> = crate::BitWriter<'a, REG, CCPC>;
46impl<'a, REG> CCPC_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///CCxE, CCxNE and OCxM bits are not preloaded
51    #[inline(always)]
52    pub fn not_preloaded(self) -> &'a mut crate::W<REG> {
53        self.variant(CCPC::NotPreloaded)
54    }
55    ///CCxE, CCxNE and OCxM bits are preloaded
56    #[inline(always)]
57    pub fn preloaded(self) -> &'a mut crate::W<REG> {
58        self.variant(CCPC::Preloaded)
59    }
60}
61/**Capture/compare control update selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CCUS {
67    ///0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
68    Sw = 0,
69    ///1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
70    SwOrEdge = 1,
71}
72impl From<CCUS> for bool {
73    #[inline(always)]
74    fn from(variant: CCUS) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCUS` reader - Capture/compare control update selection
79pub type CCUS_R = crate::BitReader<CCUS>;
80impl CCUS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CCUS {
84        match self.bits {
85            false => CCUS::Sw,
86            true => CCUS::SwOrEdge,
87        }
88    }
89    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
90    #[inline(always)]
91    pub fn is_sw(&self) -> bool {
92        *self == CCUS::Sw
93    }
94    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
95    #[inline(always)]
96    pub fn is_sw_or_edge(&self) -> bool {
97        *self == CCUS::SwOrEdge
98    }
99}
100///Field `CCUS` writer - Capture/compare control update selection
101pub type CCUS_W<'a, REG> = crate::BitWriter<'a, REG, CCUS>;
102impl<'a, REG> CCUS_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
107    #[inline(always)]
108    pub fn sw(self) -> &'a mut crate::W<REG> {
109        self.variant(CCUS::Sw)
110    }
111    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
112    #[inline(always)]
113    pub fn sw_or_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CCUS::SwOrEdge)
115    }
116}
117/**Capture/compare DMA selection
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CCDS {
123    ///0: CCx DMA request sent when CCx event occurs
124    OnCompare = 0,
125    ///1: CCx DMA request sent when update event occurs
126    OnUpdate = 1,
127}
128impl From<CCDS> for bool {
129    #[inline(always)]
130    fn from(variant: CCDS) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCDS` reader - Capture/compare DMA selection
135pub type CCDS_R = crate::BitReader<CCDS>;
136impl CCDS_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CCDS {
140        match self.bits {
141            false => CCDS::OnCompare,
142            true => CCDS::OnUpdate,
143        }
144    }
145    ///CCx DMA request sent when CCx event occurs
146    #[inline(always)]
147    pub fn is_on_compare(&self) -> bool {
148        *self == CCDS::OnCompare
149    }
150    ///CCx DMA request sent when update event occurs
151    #[inline(always)]
152    pub fn is_on_update(&self) -> bool {
153        *self == CCDS::OnUpdate
154    }
155}
156///Field `CCDS` writer - Capture/compare DMA selection
157pub type CCDS_W<'a, REG> = crate::BitWriter<'a, REG, CCDS>;
158impl<'a, REG> CCDS_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///CCx DMA request sent when CCx event occurs
163    #[inline(always)]
164    pub fn on_compare(self) -> &'a mut crate::W<REG> {
165        self.variant(CCDS::OnCompare)
166    }
167    ///CCx DMA request sent when update event occurs
168    #[inline(always)]
169    pub fn on_update(self) -> &'a mut crate::W<REG> {
170        self.variant(CCDS::OnUpdate)
171    }
172}
173///Field `MMS` reader - Master mode selection
174pub type MMS_R = crate::FieldReader;
175///Field `MMS` writer - Master mode selection
176pub type MMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
177/**Output Idle state (OC%s output)
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum OIS1 {
183    ///0: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
184    Reset = 0,
185    ///1: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
186    Set = 1,
187}
188impl From<OIS1> for bool {
189    #[inline(always)]
190    fn from(variant: OIS1) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `OIS(1-2)` reader - Output Idle state (OC%s output)
195pub type OIS_R = crate::BitReader<OIS1>;
196impl OIS_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> OIS1 {
200        match self.bits {
201            false => OIS1::Reset,
202            true => OIS1::Set,
203        }
204    }
205    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
206    #[inline(always)]
207    pub fn is_reset(&self) -> bool {
208        *self == OIS1::Reset
209    }
210    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
211    #[inline(always)]
212    pub fn is_set(&self) -> bool {
213        *self == OIS1::Set
214    }
215}
216///Field `OIS(1-2)` writer - Output Idle state (OC%s output)
217pub type OIS_W<'a, REG> = crate::BitWriter<'a, REG, OIS1>;
218impl<'a, REG> OIS_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
223    #[inline(always)]
224    pub fn reset(self) -> &'a mut crate::W<REG> {
225        self.variant(OIS1::Reset)
226    }
227    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
228    #[inline(always)]
229    pub fn set_(self) -> &'a mut crate::W<REG> {
230        self.variant(OIS1::Set)
231    }
232}
233/**Output Idle state (OC%sN output)
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum OIS1N {
239    ///0: OCxN=0 after a dead-time when MOE=0
240    Reset = 0,
241    ///1: OCxN=1 after a dead-time when MOE=0
242    Set = 1,
243}
244impl From<OIS1N> for bool {
245    #[inline(always)]
246    fn from(variant: OIS1N) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `OISN(1-1)` reader - Output Idle state (OC%sN output)
251pub type OISN_R = crate::BitReader<OIS1N>;
252impl OISN_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> OIS1N {
256        match self.bits {
257            false => OIS1N::Reset,
258            true => OIS1N::Set,
259        }
260    }
261    ///OCxN=0 after a dead-time when MOE=0
262    #[inline(always)]
263    pub fn is_reset(&self) -> bool {
264        *self == OIS1N::Reset
265    }
266    ///OCxN=1 after a dead-time when MOE=0
267    #[inline(always)]
268    pub fn is_set(&self) -> bool {
269        *self == OIS1N::Set
270    }
271}
272///Field `OISN(1-1)` writer - Output Idle state (OC%sN output)
273pub type OISN_W<'a, REG> = crate::BitWriter<'a, REG, OIS1N>;
274impl<'a, REG> OISN_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///OCxN=0 after a dead-time when MOE=0
279    #[inline(always)]
280    pub fn reset(self) -> &'a mut crate::W<REG> {
281        self.variant(OIS1N::Reset)
282    }
283    ///OCxN=1 after a dead-time when MOE=0
284    #[inline(always)]
285    pub fn set_(self) -> &'a mut crate::W<REG> {
286        self.variant(OIS1N::Set)
287    }
288}
289impl R {
290    ///Bit 0 - Capture/compare preloaded control
291    #[inline(always)]
292    pub fn ccpc(&self) -> CCPC_R {
293        CCPC_R::new((self.bits & 1) != 0)
294    }
295    ///Bit 2 - Capture/compare control update selection
296    #[inline(always)]
297    pub fn ccus(&self) -> CCUS_R {
298        CCUS_R::new(((self.bits >> 2) & 1) != 0)
299    }
300    ///Bit 3 - Capture/compare DMA selection
301    #[inline(always)]
302    pub fn ccds(&self) -> CCDS_R {
303        CCDS_R::new(((self.bits >> 3) & 1) != 0)
304    }
305    ///Bits 4:6 - Master mode selection
306    #[inline(always)]
307    pub fn mms(&self) -> MMS_R {
308        MMS_R::new(((self.bits >> 4) & 7) as u8)
309    }
310    ///Output Idle state (OC(1-2) output)
311    ///
312    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
313    #[inline(always)]
314    pub fn ois(&self, n: u8) -> OIS_R {
315        #[allow(clippy::no_effect)] [(); 2][n as usize];
316        OIS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0)
317    }
318    ///Iterator for array of:
319    ///Output Idle state (OC(1-2) output)
320    #[inline(always)]
321    pub fn ois_iter(&self) -> impl Iterator<Item = OIS_R> + '_ {
322        (0..2).map(move |n| OIS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0))
323    }
324    ///Bit 8 - Output Idle state (OC1 output)
325    #[inline(always)]
326    pub fn ois1(&self) -> OIS_R {
327        OIS_R::new(((self.bits >> 8) & 1) != 0)
328    }
329    ///Bit 10 - Output Idle state (OC2 output)
330    #[inline(always)]
331    pub fn ois2(&self) -> OIS_R {
332        OIS_R::new(((self.bits >> 10) & 1) != 0)
333    }
334    ///Output Idle state (OC(1-1)N output)
335    ///
336    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
337    #[inline(always)]
338    pub fn oisn(&self, n: u8) -> OISN_R {
339        #[allow(clippy::no_effect)] [(); 1][n as usize];
340        OISN_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0)
341    }
342    ///Iterator for array of:
343    ///Output Idle state (OC(1-1)N output)
344    #[inline(always)]
345    pub fn oisn_iter(&self) -> impl Iterator<Item = OISN_R> + '_ {
346        (0..1).map(move |n| OISN_R::new(((self.bits >> (n * 0 + 9)) & 1) != 0))
347    }
348    ///Bit 9 - Output Idle state (OC1N output)
349    #[inline(always)]
350    pub fn ois1n(&self) -> OISN_R {
351        OISN_R::new(((self.bits >> 9) & 1) != 0)
352    }
353}
354impl core::fmt::Debug for R {
355    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
356        f.debug_struct("CR2")
357            .field("ois1", &self.ois1())
358            .field("ois2", &self.ois2())
359            .field("ois1n", &self.ois1n())
360            .field("mms", &self.mms())
361            .field("ccds", &self.ccds())
362            .field("ccus", &self.ccus())
363            .field("ccpc", &self.ccpc())
364            .finish()
365    }
366}
367impl W {
368    ///Bit 0 - Capture/compare preloaded control
369    #[inline(always)]
370    pub fn ccpc(&mut self) -> CCPC_W<CR2rs> {
371        CCPC_W::new(self, 0)
372    }
373    ///Bit 2 - Capture/compare control update selection
374    #[inline(always)]
375    pub fn ccus(&mut self) -> CCUS_W<CR2rs> {
376        CCUS_W::new(self, 2)
377    }
378    ///Bit 3 - Capture/compare DMA selection
379    #[inline(always)]
380    pub fn ccds(&mut self) -> CCDS_W<CR2rs> {
381        CCDS_W::new(self, 3)
382    }
383    ///Bits 4:6 - Master mode selection
384    #[inline(always)]
385    pub fn mms(&mut self) -> MMS_W<CR2rs> {
386        MMS_W::new(self, 4)
387    }
388    ///Output Idle state (OC(1-2) output)
389    ///
390    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
391    #[inline(always)]
392    pub fn ois(&mut self, n: u8) -> OIS_W<CR2rs> {
393        #[allow(clippy::no_effect)] [(); 2][n as usize];
394        OIS_W::new(self, n * 2 + 8)
395    }
396    ///Bit 8 - Output Idle state (OC1 output)
397    #[inline(always)]
398    pub fn ois1(&mut self) -> OIS_W<CR2rs> {
399        OIS_W::new(self, 8)
400    }
401    ///Bit 10 - Output Idle state (OC2 output)
402    #[inline(always)]
403    pub fn ois2(&mut self) -> OIS_W<CR2rs> {
404        OIS_W::new(self, 10)
405    }
406    ///Output Idle state (OC(1-1)N output)
407    ///
408    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
409    #[inline(always)]
410    pub fn oisn(&mut self, n: u8) -> OISN_W<CR2rs> {
411        #[allow(clippy::no_effect)] [(); 1][n as usize];
412        OISN_W::new(self, n * 0 + 9)
413    }
414    ///Bit 9 - Output Idle state (OC1N output)
415    #[inline(always)]
416    pub fn ois1n(&mut self) -> OISN_W<CR2rs> {
417        OISN_W::new(self, 9)
418    }
419}
420/**control register 2
421
422You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
423
424See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM15:CR2)*/
425pub struct CR2rs;
426impl crate::RegisterSpec for CR2rs {
427    type Ux = u32;
428}
429///`read()` method returns [`cr2::R`](R) reader structure
430impl crate::Readable for CR2rs {}
431///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
432impl crate::Writable for CR2rs {
433    type Safety = crate::Unsafe;
434}
435///`reset()` method sets CR2 to value 0
436impl crate::Resettable for CR2rs {}
stm32f1_staging/stm32f100/tim15/cr2.rs

stm32f1_staging/stm32f100/tim15/
cr2.rs
