stm32f1_staging/stm32f100/rcc/
csr.rs

1///Register `CSR` reader
2pub type R = crate::R<CSRrs>;
3///Register `CSR` writer
4pub type W = crate::W<CSRrs>;
5/**Internal low speed oscillator enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LSION {
11    ///0: LSI oscillator Off
12    Off = 0,
13    ///1: LSI oscillator On
14    On = 1,
15}
16impl From<LSION> for bool {
17    #[inline(always)]
18    fn from(variant: LSION) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LSION` reader - Internal low speed oscillator enable
23pub type LSION_R = crate::BitReader<LSION>;
24impl LSION_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LSION {
28        match self.bits {
29            false => LSION::Off,
30            true => LSION::On,
31        }
32    }
33    ///LSI oscillator Off
34    #[inline(always)]
35    pub fn is_off(&self) -> bool {
36        *self == LSION::Off
37    }
38    ///LSI oscillator On
39    #[inline(always)]
40    pub fn is_on(&self) -> bool {
41        *self == LSION::On
42    }
43}
44///Field `LSION` writer - Internal low speed oscillator enable
45pub type LSION_W<'a, REG> = crate::BitWriter<'a, REG, LSION>;
46impl<'a, REG> LSION_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///LSI oscillator Off
51    #[inline(always)]
52    pub fn off(self) -> &'a mut crate::W<REG> {
53        self.variant(LSION::Off)
54    }
55    ///LSI oscillator On
56    #[inline(always)]
57    pub fn on(self) -> &'a mut crate::W<REG> {
58        self.variant(LSION::On)
59    }
60}
61/**Internal low speed oscillator ready
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum LSIRDYR {
67    ///0: LSI oscillator not ready
68    NotReady = 0,
69    ///1: LSI oscillator ready
70    Ready = 1,
71}
72impl From<LSIRDYR> for bool {
73    #[inline(always)]
74    fn from(variant: LSIRDYR) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `LSIRDY` reader - Internal low speed oscillator ready
79pub type LSIRDY_R = crate::BitReader<LSIRDYR>;
80impl LSIRDY_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> LSIRDYR {
84        match self.bits {
85            false => LSIRDYR::NotReady,
86            true => LSIRDYR::Ready,
87        }
88    }
89    ///LSI oscillator not ready
90    #[inline(always)]
91    pub fn is_not_ready(&self) -> bool {
92        *self == LSIRDYR::NotReady
93    }
94    ///LSI oscillator ready
95    #[inline(always)]
96    pub fn is_ready(&self) -> bool {
97        *self == LSIRDYR::Ready
98    }
99}
100/**Remove reset flag
101
102Value on reset: 0*/
103#[cfg_attr(feature = "defmt", derive(defmt::Format))]
104#[derive(Clone, Copy, Debug, PartialEq, Eq)]
105pub enum RMVFW {
106    ///1: Clears the reset flag
107    Clear = 1,
108}
109impl From<RMVFW> for bool {
110    #[inline(always)]
111    fn from(variant: RMVFW) -> Self {
112        variant as u8 != 0
113    }
114}
115///Field `RMVF` reader - Remove reset flag
116pub type RMVF_R = crate::BitReader<RMVFW>;
117impl RMVF_R {
118    ///Get enumerated values variant
119    #[inline(always)]
120    pub const fn variant(&self) -> Option<RMVFW> {
121        match self.bits {
122            true => Some(RMVFW::Clear),
123            _ => None,
124        }
125    }
126    ///Clears the reset flag
127    #[inline(always)]
128    pub fn is_clear(&self) -> bool {
129        *self == RMVFW::Clear
130    }
131}
132///Field `RMVF` writer - Remove reset flag
133pub type RMVF_W<'a, REG> = crate::BitWriter<'a, REG, RMVFW>;
134impl<'a, REG> RMVF_W<'a, REG>
135where
136    REG: crate::Writable + crate::RegisterSpec,
137{
138    ///Clears the reset flag
139    #[inline(always)]
140    pub fn clear(self) -> &'a mut crate::W<REG> {
141        self.variant(RMVFW::Clear)
142    }
143}
144/**PIN reset flag
145
146Value on reset: 1*/
147#[cfg_attr(feature = "defmt", derive(defmt::Format))]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149pub enum PINRSTFR {
150    ///0: No reset has occured
151    NoReset = 0,
152    ///1: A reset has occured
153    Reset = 1,
154}
155impl From<PINRSTFR> for bool {
156    #[inline(always)]
157    fn from(variant: PINRSTFR) -> Self {
158        variant as u8 != 0
159    }
160}
161///Field `PINRSTF` reader - PIN reset flag
162pub type PINRSTF_R = crate::BitReader<PINRSTFR>;
163impl PINRSTF_R {
164    ///Get enumerated values variant
165    #[inline(always)]
166    pub const fn variant(&self) -> PINRSTFR {
167        match self.bits {
168            false => PINRSTFR::NoReset,
169            true => PINRSTFR::Reset,
170        }
171    }
172    ///No reset has occured
173    #[inline(always)]
174    pub fn is_no_reset(&self) -> bool {
175        *self == PINRSTFR::NoReset
176    }
177    ///A reset has occured
178    #[inline(always)]
179    pub fn is_reset(&self) -> bool {
180        *self == PINRSTFR::Reset
181    }
182}
183///Field `PINRSTF` writer - PIN reset flag
184pub type PINRSTF_W<'a, REG> = crate::BitWriter<'a, REG, PINRSTFR>;
185impl<'a, REG> PINRSTF_W<'a, REG>
186where
187    REG: crate::Writable + crate::RegisterSpec,
188{
189    ///No reset has occured
190    #[inline(always)]
191    pub fn no_reset(self) -> &'a mut crate::W<REG> {
192        self.variant(PINRSTFR::NoReset)
193    }
194    ///A reset has occured
195    #[inline(always)]
196    pub fn reset(self) -> &'a mut crate::W<REG> {
197        self.variant(PINRSTFR::Reset)
198    }
199}
200///Field `PORRSTF` reader - POR/PDR reset flag
201pub use PINRSTF_R as PORRSTF_R;
202///Field `SFTRSTF` reader - Software reset flag
203pub use PINRSTF_R as SFTRSTF_R;
204///Field `IWDGRSTF` reader - Independent watchdog reset flag
205pub use PINRSTF_R as IWDGRSTF_R;
206///Field `WWDGRSTF` reader - Window watchdog reset flag
207pub use PINRSTF_R as WWDGRSTF_R;
208///Field `LPWRRSTF` reader - Low-power reset flag
209pub use PINRSTF_R as LPWRRSTF_R;
210///Field `PORRSTF` writer - POR/PDR reset flag
211pub use PINRSTF_W as PORRSTF_W;
212///Field `SFTRSTF` writer - Software reset flag
213pub use PINRSTF_W as SFTRSTF_W;
214///Field `IWDGRSTF` writer - Independent watchdog reset flag
215pub use PINRSTF_W as IWDGRSTF_W;
216///Field `WWDGRSTF` writer - Window watchdog reset flag
217pub use PINRSTF_W as WWDGRSTF_W;
218///Field `LPWRRSTF` writer - Low-power reset flag
219pub use PINRSTF_W as LPWRRSTF_W;
220impl R {
221    ///Bit 0 - Internal low speed oscillator enable
222    #[inline(always)]
223    pub fn lsion(&self) -> LSION_R {
224        LSION_R::new((self.bits & 1) != 0)
225    }
226    ///Bit 1 - Internal low speed oscillator ready
227    #[inline(always)]
228    pub fn lsirdy(&self) -> LSIRDY_R {
229        LSIRDY_R::new(((self.bits >> 1) & 1) != 0)
230    }
231    ///Bit 24 - Remove reset flag
232    #[inline(always)]
233    pub fn rmvf(&self) -> RMVF_R {
234        RMVF_R::new(((self.bits >> 24) & 1) != 0)
235    }
236    ///Bit 26 - PIN reset flag
237    #[inline(always)]
238    pub fn pinrstf(&self) -> PINRSTF_R {
239        PINRSTF_R::new(((self.bits >> 26) & 1) != 0)
240    }
241    ///Bit 27 - POR/PDR reset flag
242    #[inline(always)]
243    pub fn porrstf(&self) -> PORRSTF_R {
244        PORRSTF_R::new(((self.bits >> 27) & 1) != 0)
245    }
246    ///Bit 28 - Software reset flag
247    #[inline(always)]
248    pub fn sftrstf(&self) -> SFTRSTF_R {
249        SFTRSTF_R::new(((self.bits >> 28) & 1) != 0)
250    }
251    ///Bit 29 - Independent watchdog reset flag
252    #[inline(always)]
253    pub fn iwdgrstf(&self) -> IWDGRSTF_R {
254        IWDGRSTF_R::new(((self.bits >> 29) & 1) != 0)
255    }
256    ///Bit 30 - Window watchdog reset flag
257    #[inline(always)]
258    pub fn wwdgrstf(&self) -> WWDGRSTF_R {
259        WWDGRSTF_R::new(((self.bits >> 30) & 1) != 0)
260    }
261    ///Bit 31 - Low-power reset flag
262    #[inline(always)]
263    pub fn lpwrrstf(&self) -> LPWRRSTF_R {
264        LPWRRSTF_R::new(((self.bits >> 31) & 1) != 0)
265    }
266}
267impl core::fmt::Debug for R {
268    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
269        f.debug_struct("CSR")
270            .field("lsion", &self.lsion())
271            .field("lsirdy", &self.lsirdy())
272            .field("rmvf", &self.rmvf())
273            .field("pinrstf", &self.pinrstf())
274            .field("porrstf", &self.porrstf())
275            .field("sftrstf", &self.sftrstf())
276            .field("iwdgrstf", &self.iwdgrstf())
277            .field("wwdgrstf", &self.wwdgrstf())
278            .field("lpwrrstf", &self.lpwrrstf())
279            .finish()
280    }
281}
282impl W {
283    ///Bit 0 - Internal low speed oscillator enable
284    #[inline(always)]
285    pub fn lsion(&mut self) -> LSION_W<CSRrs> {
286        LSION_W::new(self, 0)
287    }
288    ///Bit 24 - Remove reset flag
289    #[inline(always)]
290    pub fn rmvf(&mut self) -> RMVF_W<CSRrs> {
291        RMVF_W::new(self, 24)
292    }
293    ///Bit 26 - PIN reset flag
294    #[inline(always)]
295    pub fn pinrstf(&mut self) -> PINRSTF_W<CSRrs> {
296        PINRSTF_W::new(self, 26)
297    }
298    ///Bit 27 - POR/PDR reset flag
299    #[inline(always)]
300    pub fn porrstf(&mut self) -> PORRSTF_W<CSRrs> {
301        PORRSTF_W::new(self, 27)
302    }
303    ///Bit 28 - Software reset flag
304    #[inline(always)]
305    pub fn sftrstf(&mut self) -> SFTRSTF_W<CSRrs> {
306        SFTRSTF_W::new(self, 28)
307    }
308    ///Bit 29 - Independent watchdog reset flag
309    #[inline(always)]
310    pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<CSRrs> {
311        IWDGRSTF_W::new(self, 29)
312    }
313    ///Bit 30 - Window watchdog reset flag
314    #[inline(always)]
315    pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<CSRrs> {
316        WWDGRSTF_W::new(self, 30)
317    }
318    ///Bit 31 - Low-power reset flag
319    #[inline(always)]
320    pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<CSRrs> {
321        LPWRRSTF_W::new(self, 31)
322    }
323}
324/**Control/status register (RCC_CSR)
325
326You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
327
328See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RCC:CSR)*/
329pub struct CSRrs;
330impl crate::RegisterSpec for CSRrs {
331    type Ux = u32;
332}
333///`read()` method returns [`csr::R`](R) reader structure
334impl crate::Readable for CSRrs {}
335///`write(|w| ..)` method takes [`csr::W`](W) writer structure
336impl crate::Writable for CSRrs {
337    type Safety = crate::Unsafe;
338}
339///`reset()` method sets CSR to value 0x0c00_0000
340impl crate::Resettable for CSRrs {
341    const RESET_VALUE: u32 = 0x0c00_0000;
342}
stm32f1_staging/stm32f100/rcc/csr.rs

stm32f1_staging/stm32f100/rcc/
csr.rs
