stm32f1_staging/stm32f100/rcc/
apb2rstr.rs

1///Register `APB2RSTR` reader
2pub type R = crate::R<APB2RSTRrs>;
3///Register `APB2RSTR` writer
4pub type W = crate::W<APB2RSTRrs>;
5/**Alternate function I/O reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIORST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<AFIORST> for bool {
15    #[inline(always)]
16    fn from(variant: AFIORST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `AFIORST` reader - Alternate function I/O reset
21pub type AFIORST_R = crate::BitReader<AFIORST>;
22impl AFIORST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<AFIORST> {
26        match self.bits {
27            true => Some(AFIORST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == AFIORST::Reset
35    }
36}
37///Field `AFIORST` writer - Alternate function I/O reset
38pub type AFIORST_W<'a, REG> = crate::BitWriter<'a, REG, AFIORST>;
39impl<'a, REG> AFIORST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(AFIORST::Reset)
47    }
48}
49///Field `IOPARST` reader - IO port A reset
50pub use AFIORST_R as IOPARST_R;
51///Field `IOPBRST` reader - IO port B reset
52pub use AFIORST_R as IOPBRST_R;
53///Field `IOPCRST` reader - IO port C reset
54pub use AFIORST_R as IOPCRST_R;
55///Field `IOPDRST` reader - IO port D reset
56pub use AFIORST_R as IOPDRST_R;
57///Field `IOPERST` reader - IO port E reset
58pub use AFIORST_R as IOPERST_R;
59///Field `IOPFRST` reader - IO port F reset
60pub use AFIORST_R as IOPFRST_R;
61///Field `IOPGRST` reader - IO port G reset
62pub use AFIORST_R as IOPGRST_R;
63///Field `ADC1RST` reader - ADC 1 interface reset
64pub use AFIORST_R as ADC1RST_R;
65///Field `TIM1RST` reader - TIM1 timer reset
66pub use AFIORST_R as TIM1RST_R;
67///Field `SPI1RST` reader - SPI 1 reset
68pub use AFIORST_R as SPI1RST_R;
69///Field `USART1RST` reader - USART1 reset
70pub use AFIORST_R as USART1RST_R;
71///Field `TIM15RST` reader - TIM15 timer reset
72pub use AFIORST_R as TIM15RST_R;
73///Field `TIM16RST` reader - TIM16 timer reset
74pub use AFIORST_R as TIM16RST_R;
75///Field `TIM17RST` reader - TIM17 timer reset
76pub use AFIORST_R as TIM17RST_R;
77///Field `IOPARST` writer - IO port A reset
78pub use AFIORST_W as IOPARST_W;
79///Field `IOPBRST` writer - IO port B reset
80pub use AFIORST_W as IOPBRST_W;
81///Field `IOPCRST` writer - IO port C reset
82pub use AFIORST_W as IOPCRST_W;
83///Field `IOPDRST` writer - IO port D reset
84pub use AFIORST_W as IOPDRST_W;
85///Field `IOPERST` writer - IO port E reset
86pub use AFIORST_W as IOPERST_W;
87///Field `IOPFRST` writer - IO port F reset
88pub use AFIORST_W as IOPFRST_W;
89///Field `IOPGRST` writer - IO port G reset
90pub use AFIORST_W as IOPGRST_W;
91///Field `ADC1RST` writer - ADC 1 interface reset
92pub use AFIORST_W as ADC1RST_W;
93///Field `TIM1RST` writer - TIM1 timer reset
94pub use AFIORST_W as TIM1RST_W;
95///Field `SPI1RST` writer - SPI 1 reset
96pub use AFIORST_W as SPI1RST_W;
97///Field `USART1RST` writer - USART1 reset
98pub use AFIORST_W as USART1RST_W;
99///Field `TIM15RST` writer - TIM15 timer reset
100pub use AFIORST_W as TIM15RST_W;
101///Field `TIM16RST` writer - TIM16 timer reset
102pub use AFIORST_W as TIM16RST_W;
103///Field `TIM17RST` writer - TIM17 timer reset
104pub use AFIORST_W as TIM17RST_W;
105impl R {
106    ///Bit 0 - Alternate function I/O reset
107    #[inline(always)]
108    pub fn afiorst(&self) -> AFIORST_R {
109        AFIORST_R::new((self.bits & 1) != 0)
110    }
111    ///Bit 2 - IO port A reset
112    #[inline(always)]
113    pub fn ioparst(&self) -> IOPARST_R {
114        IOPARST_R::new(((self.bits >> 2) & 1) != 0)
115    }
116    ///Bit 3 - IO port B reset
117    #[inline(always)]
118    pub fn iopbrst(&self) -> IOPBRST_R {
119        IOPBRST_R::new(((self.bits >> 3) & 1) != 0)
120    }
121    ///Bit 4 - IO port C reset
122    #[inline(always)]
123    pub fn iopcrst(&self) -> IOPCRST_R {
124        IOPCRST_R::new(((self.bits >> 4) & 1) != 0)
125    }
126    ///Bit 5 - IO port D reset
127    #[inline(always)]
128    pub fn iopdrst(&self) -> IOPDRST_R {
129        IOPDRST_R::new(((self.bits >> 5) & 1) != 0)
130    }
131    ///Bit 6 - IO port E reset
132    #[inline(always)]
133    pub fn ioperst(&self) -> IOPERST_R {
134        IOPERST_R::new(((self.bits >> 6) & 1) != 0)
135    }
136    ///Bit 7 - IO port F reset
137    #[inline(always)]
138    pub fn iopfrst(&self) -> IOPFRST_R {
139        IOPFRST_R::new(((self.bits >> 7) & 1) != 0)
140    }
141    ///Bit 8 - IO port G reset
142    #[inline(always)]
143    pub fn iopgrst(&self) -> IOPGRST_R {
144        IOPGRST_R::new(((self.bits >> 8) & 1) != 0)
145    }
146    ///Bit 9 - ADC 1 interface reset
147    #[inline(always)]
148    pub fn adc1rst(&self) -> ADC1RST_R {
149        ADC1RST_R::new(((self.bits >> 9) & 1) != 0)
150    }
151    ///Bit 11 - TIM1 timer reset
152    #[inline(always)]
153    pub fn tim1rst(&self) -> TIM1RST_R {
154        TIM1RST_R::new(((self.bits >> 11) & 1) != 0)
155    }
156    ///Bit 12 - SPI 1 reset
157    #[inline(always)]
158    pub fn spi1rst(&self) -> SPI1RST_R {
159        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
160    }
161    ///Bit 14 - USART1 reset
162    #[inline(always)]
163    pub fn usart1rst(&self) -> USART1RST_R {
164        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
165    }
166    ///Bit 16 - TIM15 timer reset
167    #[inline(always)]
168    pub fn tim15rst(&self) -> TIM15RST_R {
169        TIM15RST_R::new(((self.bits >> 16) & 1) != 0)
170    }
171    ///Bit 17 - TIM16 timer reset
172    #[inline(always)]
173    pub fn tim16rst(&self) -> TIM16RST_R {
174        TIM16RST_R::new(((self.bits >> 17) & 1) != 0)
175    }
176    ///Bit 18 - TIM17 timer reset
177    #[inline(always)]
178    pub fn tim17rst(&self) -> TIM17RST_R {
179        TIM17RST_R::new(((self.bits >> 18) & 1) != 0)
180    }
181}
182impl core::fmt::Debug for R {
183    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
184        f.debug_struct("APB2RSTR")
185            .field("afiorst", &self.afiorst())
186            .field("ioparst", &self.ioparst())
187            .field("iopbrst", &self.iopbrst())
188            .field("iopcrst", &self.iopcrst())
189            .field("iopdrst", &self.iopdrst())
190            .field("ioperst", &self.ioperst())
191            .field("iopfrst", &self.iopfrst())
192            .field("iopgrst", &self.iopgrst())
193            .field("adc1rst", &self.adc1rst())
194            .field("tim1rst", &self.tim1rst())
195            .field("spi1rst", &self.spi1rst())
196            .field("usart1rst", &self.usart1rst())
197            .field("tim15rst", &self.tim15rst())
198            .field("tim16rst", &self.tim16rst())
199            .field("tim17rst", &self.tim17rst())
200            .finish()
201    }
202}
203impl W {
204    ///Bit 0 - Alternate function I/O reset
205    #[inline(always)]
206    pub fn afiorst(&mut self) -> AFIORST_W<APB2RSTRrs> {
207        AFIORST_W::new(self, 0)
208    }
209    ///Bit 2 - IO port A reset
210    #[inline(always)]
211    pub fn ioparst(&mut self) -> IOPARST_W<APB2RSTRrs> {
212        IOPARST_W::new(self, 2)
213    }
214    ///Bit 3 - IO port B reset
215    #[inline(always)]
216    pub fn iopbrst(&mut self) -> IOPBRST_W<APB2RSTRrs> {
217        IOPBRST_W::new(self, 3)
218    }
219    ///Bit 4 - IO port C reset
220    #[inline(always)]
221    pub fn iopcrst(&mut self) -> IOPCRST_W<APB2RSTRrs> {
222        IOPCRST_W::new(self, 4)
223    }
224    ///Bit 5 - IO port D reset
225    #[inline(always)]
226    pub fn iopdrst(&mut self) -> IOPDRST_W<APB2RSTRrs> {
227        IOPDRST_W::new(self, 5)
228    }
229    ///Bit 6 - IO port E reset
230    #[inline(always)]
231    pub fn ioperst(&mut self) -> IOPERST_W<APB2RSTRrs> {
232        IOPERST_W::new(self, 6)
233    }
234    ///Bit 7 - IO port F reset
235    #[inline(always)]
236    pub fn iopfrst(&mut self) -> IOPFRST_W<APB2RSTRrs> {
237        IOPFRST_W::new(self, 7)
238    }
239    ///Bit 8 - IO port G reset
240    #[inline(always)]
241    pub fn iopgrst(&mut self) -> IOPGRST_W<APB2RSTRrs> {
242        IOPGRST_W::new(self, 8)
243    }
244    ///Bit 9 - ADC 1 interface reset
245    #[inline(always)]
246    pub fn adc1rst(&mut self) -> ADC1RST_W<APB2RSTRrs> {
247        ADC1RST_W::new(self, 9)
248    }
249    ///Bit 11 - TIM1 timer reset
250    #[inline(always)]
251    pub fn tim1rst(&mut self) -> TIM1RST_W<APB2RSTRrs> {
252        TIM1RST_W::new(self, 11)
253    }
254    ///Bit 12 - SPI 1 reset
255    #[inline(always)]
256    pub fn spi1rst(&mut self) -> SPI1RST_W<APB2RSTRrs> {
257        SPI1RST_W::new(self, 12)
258    }
259    ///Bit 14 - USART1 reset
260    #[inline(always)]
261    pub fn usart1rst(&mut self) -> USART1RST_W<APB2RSTRrs> {
262        USART1RST_W::new(self, 14)
263    }
264    ///Bit 16 - TIM15 timer reset
265    #[inline(always)]
266    pub fn tim15rst(&mut self) -> TIM15RST_W<APB2RSTRrs> {
267        TIM15RST_W::new(self, 16)
268    }
269    ///Bit 17 - TIM16 timer reset
270    #[inline(always)]
271    pub fn tim16rst(&mut self) -> TIM16RST_W<APB2RSTRrs> {
272        TIM16RST_W::new(self, 17)
273    }
274    ///Bit 18 - TIM17 timer reset
275    #[inline(always)]
276    pub fn tim17rst(&mut self) -> TIM17RST_W<APB2RSTRrs> {
277        TIM17RST_W::new(self, 18)
278    }
279}
280/**APB2 peripheral reset register (RCC_APB2RSTR)
281
282You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
283
284See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RCC:APB2RSTR)*/
285pub struct APB2RSTRrs;
286impl crate::RegisterSpec for APB2RSTRrs {
287    type Ux = u32;
288}
289///`read()` method returns [`apb2rstr::R`](R) reader structure
290impl crate::Readable for APB2RSTRrs {}
291///`write(|w| ..)` method takes [`apb2rstr::W`](W) writer structure
292impl crate::Writable for APB2RSTRrs {
293    type Safety = crate::Unsafe;
294}
295///`reset()` method sets APB2RSTR to value 0
296impl crate::Resettable for APB2RSTRrs {}
stm32f1_staging/stm32f100/rcc/apb2rstr.rs

stm32f1_staging/stm32f100/rcc/
apb2rstr.rs
