stm32f1_staging/stm32f100/rcc/
apb2enr.rs

1///Register `APB2ENR` reader
2pub type R = crate::R<APB2ENRrs>;
3///Register `APB2ENR` writer
4pub type W = crate::W<APB2ENRrs>;
5/**Alternate function I/O clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIOEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<AFIOEN> for bool {
17    #[inline(always)]
18    fn from(variant: AFIOEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AFIOEN` reader - Alternate function I/O clock enable
23pub type AFIOEN_R = crate::BitReader<AFIOEN>;
24impl AFIOEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AFIOEN {
28        match self.bits {
29            false => AFIOEN::Disabled,
30            true => AFIOEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == AFIOEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == AFIOEN::Enabled
42    }
43}
44///Field `AFIOEN` writer - Alternate function I/O clock enable
45pub type AFIOEN_W<'a, REG> = crate::BitWriter<'a, REG, AFIOEN>;
46impl<'a, REG> AFIOEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(AFIOEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(AFIOEN::Enabled)
59    }
60}
61///Field `IOPAEN` reader - I/O port A clock enable
62pub use AFIOEN_R as IOPAEN_R;
63///Field `IOPBEN` reader - I/O port B clock enable
64pub use AFIOEN_R as IOPBEN_R;
65///Field `IOPCEN` reader - I/O port C clock enable
66pub use AFIOEN_R as IOPCEN_R;
67///Field `IOPDEN` reader - I/O port D clock enable
68pub use AFIOEN_R as IOPDEN_R;
69///Field `IOPEEN` reader - I/O port E clock enable
70pub use AFIOEN_R as IOPEEN_R;
71///Field `IOPFEN` reader - I/O port F clock enable
72pub use AFIOEN_R as IOPFEN_R;
73///Field `IOPGEN` reader - I/O port G clock enable
74pub use AFIOEN_R as IOPGEN_R;
75///Field `ADC1EN` reader - ADC 1 interface clock enable
76pub use AFIOEN_R as ADC1EN_R;
77///Field `TIM1EN` reader - TIM1 Timer clock enable
78pub use AFIOEN_R as TIM1EN_R;
79///Field `SPI1EN` reader - SPI 1 clock enable
80pub use AFIOEN_R as SPI1EN_R;
81///Field `USART1EN` reader - USART1 clock enable
82pub use AFIOEN_R as USART1EN_R;
83///Field `TIM15EN` reader - TIM15 Timer clock enable
84pub use AFIOEN_R as TIM15EN_R;
85///Field `TIM16EN` reader - TIM16 Timer clock enable
86pub use AFIOEN_R as TIM16EN_R;
87///Field `TIM17EN` reader - TIM17 Timer clock enable
88pub use AFIOEN_R as TIM17EN_R;
89///Field `IOPAEN` writer - I/O port A clock enable
90pub use AFIOEN_W as IOPAEN_W;
91///Field `IOPBEN` writer - I/O port B clock enable
92pub use AFIOEN_W as IOPBEN_W;
93///Field `IOPCEN` writer - I/O port C clock enable
94pub use AFIOEN_W as IOPCEN_W;
95///Field `IOPDEN` writer - I/O port D clock enable
96pub use AFIOEN_W as IOPDEN_W;
97///Field `IOPEEN` writer - I/O port E clock enable
98pub use AFIOEN_W as IOPEEN_W;
99///Field `IOPFEN` writer - I/O port F clock enable
100pub use AFIOEN_W as IOPFEN_W;
101///Field `IOPGEN` writer - I/O port G clock enable
102pub use AFIOEN_W as IOPGEN_W;
103///Field `ADC1EN` writer - ADC 1 interface clock enable
104pub use AFIOEN_W as ADC1EN_W;
105///Field `TIM1EN` writer - TIM1 Timer clock enable
106pub use AFIOEN_W as TIM1EN_W;
107///Field `SPI1EN` writer - SPI 1 clock enable
108pub use AFIOEN_W as SPI1EN_W;
109///Field `USART1EN` writer - USART1 clock enable
110pub use AFIOEN_W as USART1EN_W;
111///Field `TIM15EN` writer - TIM15 Timer clock enable
112pub use AFIOEN_W as TIM15EN_W;
113///Field `TIM16EN` writer - TIM16 Timer clock enable
114pub use AFIOEN_W as TIM16EN_W;
115///Field `TIM17EN` writer - TIM17 Timer clock enable
116pub use AFIOEN_W as TIM17EN_W;
117impl R {
118    ///Bit 0 - Alternate function I/O clock enable
119    #[inline(always)]
120    pub fn afioen(&self) -> AFIOEN_R {
121        AFIOEN_R::new((self.bits & 1) != 0)
122    }
123    ///Bit 2 - I/O port A clock enable
124    #[inline(always)]
125    pub fn iopaen(&self) -> IOPAEN_R {
126        IOPAEN_R::new(((self.bits >> 2) & 1) != 0)
127    }
128    ///Bit 3 - I/O port B clock enable
129    #[inline(always)]
130    pub fn iopben(&self) -> IOPBEN_R {
131        IOPBEN_R::new(((self.bits >> 3) & 1) != 0)
132    }
133    ///Bit 4 - I/O port C clock enable
134    #[inline(always)]
135    pub fn iopcen(&self) -> IOPCEN_R {
136        IOPCEN_R::new(((self.bits >> 4) & 1) != 0)
137    }
138    ///Bit 5 - I/O port D clock enable
139    #[inline(always)]
140    pub fn iopden(&self) -> IOPDEN_R {
141        IOPDEN_R::new(((self.bits >> 5) & 1) != 0)
142    }
143    ///Bit 6 - I/O port E clock enable
144    #[inline(always)]
145    pub fn iopeen(&self) -> IOPEEN_R {
146        IOPEEN_R::new(((self.bits >> 6) & 1) != 0)
147    }
148    ///Bit 7 - I/O port F clock enable
149    #[inline(always)]
150    pub fn iopfen(&self) -> IOPFEN_R {
151        IOPFEN_R::new(((self.bits >> 7) & 1) != 0)
152    }
153    ///Bit 8 - I/O port G clock enable
154    #[inline(always)]
155    pub fn iopgen(&self) -> IOPGEN_R {
156        IOPGEN_R::new(((self.bits >> 8) & 1) != 0)
157    }
158    ///Bit 9 - ADC 1 interface clock enable
159    #[inline(always)]
160    pub fn adc1en(&self) -> ADC1EN_R {
161        ADC1EN_R::new(((self.bits >> 9) & 1) != 0)
162    }
163    ///Bit 11 - TIM1 Timer clock enable
164    #[inline(always)]
165    pub fn tim1en(&self) -> TIM1EN_R {
166        TIM1EN_R::new(((self.bits >> 11) & 1) != 0)
167    }
168    ///Bit 12 - SPI 1 clock enable
169    #[inline(always)]
170    pub fn spi1en(&self) -> SPI1EN_R {
171        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
172    }
173    ///Bit 14 - USART1 clock enable
174    #[inline(always)]
175    pub fn usart1en(&self) -> USART1EN_R {
176        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
177    }
178    ///Bit 16 - TIM15 Timer clock enable
179    #[inline(always)]
180    pub fn tim15en(&self) -> TIM15EN_R {
181        TIM15EN_R::new(((self.bits >> 16) & 1) != 0)
182    }
183    ///Bit 17 - TIM16 Timer clock enable
184    #[inline(always)]
185    pub fn tim16en(&self) -> TIM16EN_R {
186        TIM16EN_R::new(((self.bits >> 17) & 1) != 0)
187    }
188    ///Bit 18 - TIM17 Timer clock enable
189    #[inline(always)]
190    pub fn tim17en(&self) -> TIM17EN_R {
191        TIM17EN_R::new(((self.bits >> 18) & 1) != 0)
192    }
193}
194impl core::fmt::Debug for R {
195    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
196        f.debug_struct("APB2ENR")
197            .field("afioen", &self.afioen())
198            .field("iopaen", &self.iopaen())
199            .field("iopben", &self.iopben())
200            .field("iopcen", &self.iopcen())
201            .field("iopden", &self.iopden())
202            .field("iopeen", &self.iopeen())
203            .field("iopfen", &self.iopfen())
204            .field("iopgen", &self.iopgen())
205            .field("adc1en", &self.adc1en())
206            .field("tim1en", &self.tim1en())
207            .field("spi1en", &self.spi1en())
208            .field("usart1en", &self.usart1en())
209            .field("tim15en", &self.tim15en())
210            .field("tim16en", &self.tim16en())
211            .field("tim17en", &self.tim17en())
212            .finish()
213    }
214}
215impl W {
216    ///Bit 0 - Alternate function I/O clock enable
217    #[inline(always)]
218    pub fn afioen(&mut self) -> AFIOEN_W<APB2ENRrs> {
219        AFIOEN_W::new(self, 0)
220    }
221    ///Bit 2 - I/O port A clock enable
222    #[inline(always)]
223    pub fn iopaen(&mut self) -> IOPAEN_W<APB2ENRrs> {
224        IOPAEN_W::new(self, 2)
225    }
226    ///Bit 3 - I/O port B clock enable
227    #[inline(always)]
228    pub fn iopben(&mut self) -> IOPBEN_W<APB2ENRrs> {
229        IOPBEN_W::new(self, 3)
230    }
231    ///Bit 4 - I/O port C clock enable
232    #[inline(always)]
233    pub fn iopcen(&mut self) -> IOPCEN_W<APB2ENRrs> {
234        IOPCEN_W::new(self, 4)
235    }
236    ///Bit 5 - I/O port D clock enable
237    #[inline(always)]
238    pub fn iopden(&mut self) -> IOPDEN_W<APB2ENRrs> {
239        IOPDEN_W::new(self, 5)
240    }
241    ///Bit 6 - I/O port E clock enable
242    #[inline(always)]
243    pub fn iopeen(&mut self) -> IOPEEN_W<APB2ENRrs> {
244        IOPEEN_W::new(self, 6)
245    }
246    ///Bit 7 - I/O port F clock enable
247    #[inline(always)]
248    pub fn iopfen(&mut self) -> IOPFEN_W<APB2ENRrs> {
249        IOPFEN_W::new(self, 7)
250    }
251    ///Bit 8 - I/O port G clock enable
252    #[inline(always)]
253    pub fn iopgen(&mut self) -> IOPGEN_W<APB2ENRrs> {
254        IOPGEN_W::new(self, 8)
255    }
256    ///Bit 9 - ADC 1 interface clock enable
257    #[inline(always)]
258    pub fn adc1en(&mut self) -> ADC1EN_W<APB2ENRrs> {
259        ADC1EN_W::new(self, 9)
260    }
261    ///Bit 11 - TIM1 Timer clock enable
262    #[inline(always)]
263    pub fn tim1en(&mut self) -> TIM1EN_W<APB2ENRrs> {
264        TIM1EN_W::new(self, 11)
265    }
266    ///Bit 12 - SPI 1 clock enable
267    #[inline(always)]
268    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
269        SPI1EN_W::new(self, 12)
270    }
271    ///Bit 14 - USART1 clock enable
272    #[inline(always)]
273    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
274        USART1EN_W::new(self, 14)
275    }
276    ///Bit 16 - TIM15 Timer clock enable
277    #[inline(always)]
278    pub fn tim15en(&mut self) -> TIM15EN_W<APB2ENRrs> {
279        TIM15EN_W::new(self, 16)
280    }
281    ///Bit 17 - TIM16 Timer clock enable
282    #[inline(always)]
283    pub fn tim16en(&mut self) -> TIM16EN_W<APB2ENRrs> {
284        TIM16EN_W::new(self, 17)
285    }
286    ///Bit 18 - TIM17 Timer clock enable
287    #[inline(always)]
288    pub fn tim17en(&mut self) -> TIM17EN_W<APB2ENRrs> {
289        TIM17EN_W::new(self, 18)
290    }
291}
292/**APB2 peripheral clock enable register (RCC_APB2ENR)
293
294You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RCC:APB2ENR)*/
297pub struct APB2ENRrs;
298impl crate::RegisterSpec for APB2ENRrs {
299    type Ux = u32;
300}
301///`read()` method returns [`apb2enr::R`](R) reader structure
302impl crate::Readable for APB2ENRrs {}
303///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
304impl crate::Writable for APB2ENRrs {
305    type Safety = crate::Unsafe;
306}
307///`reset()` method sets APB2ENR to value 0
308impl crate::Resettable for APB2ENRrs {}
stm32f1_staging/stm32f100/rcc/apb2enr.rs

stm32f1_staging/stm32f100/rcc/
apb2enr.rs
