stm32f1_staging/stm32f100/exti/
emr.rs

1///Register `EMR` reader
2pub type R = crate::R<EMRrs>;
3///Register `EMR` writer
4pub type W = crate::W<EMRrs>;
5/**Event Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EVENT_MASK {
11    ///0: Event request line is masked
12    Masked = 0,
13    ///1: Event request line is unmasked
14    Unmasked = 1,
15}
16impl From<EVENT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: EVENT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR(0-17)` reader - Event Mask on line %s
23pub type MR_R = crate::BitReader<EVENT_MASK>;
24impl MR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EVENT_MASK {
28        match self.bits {
29            false => EVENT_MASK::Masked,
30            true => EVENT_MASK::Unmasked,
31        }
32    }
33    ///Event request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == EVENT_MASK::Masked
37    }
38    ///Event request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == EVENT_MASK::Unmasked
42    }
43}
44///Field `MR(0-17)` writer - Event Mask on line %s
45pub type MR_W<'a, REG> = crate::BitWriter<'a, REG, EVENT_MASK>;
46impl<'a, REG> MR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Event request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(EVENT_MASK::Masked)
54    }
55    ///Event request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(EVENT_MASK::Unmasked)
59    }
60}
61impl R {
62    ///Event Mask on line (0-17)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
65    #[inline(always)]
66    pub fn mr(&self, n: u8) -> MR_R {
67        #[allow(clippy::no_effect)] [(); 18][n as usize];
68        MR_R::new(((self.bits >> n) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Event Mask on line (0-17)
72    #[inline(always)]
73    pub fn mr_iter(&self) -> impl Iterator<Item = MR_R> + '_ {
74        (0..18).map(move |n| MR_R::new(((self.bits >> n) & 1) != 0))
75    }
76    ///Bit 0 - Event Mask on line 0
77    #[inline(always)]
78    pub fn mr0(&self) -> MR_R {
79        MR_R::new((self.bits & 1) != 0)
80    }
81    ///Bit 1 - Event Mask on line 1
82    #[inline(always)]
83    pub fn mr1(&self) -> MR_R {
84        MR_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    ///Bit 2 - Event Mask on line 2
87    #[inline(always)]
88    pub fn mr2(&self) -> MR_R {
89        MR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    ///Bit 3 - Event Mask on line 3
92    #[inline(always)]
93    pub fn mr3(&self) -> MR_R {
94        MR_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    ///Bit 4 - Event Mask on line 4
97    #[inline(always)]
98    pub fn mr4(&self) -> MR_R {
99        MR_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    ///Bit 5 - Event Mask on line 5
102    #[inline(always)]
103    pub fn mr5(&self) -> MR_R {
104        MR_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    ///Bit 6 - Event Mask on line 6
107    #[inline(always)]
108    pub fn mr6(&self) -> MR_R {
109        MR_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 7 - Event Mask on line 7
112    #[inline(always)]
113    pub fn mr7(&self) -> MR_R {
114        MR_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    ///Bit 8 - Event Mask on line 8
117    #[inline(always)]
118    pub fn mr8(&self) -> MR_R {
119        MR_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    ///Bit 9 - Event Mask on line 9
122    #[inline(always)]
123    pub fn mr9(&self) -> MR_R {
124        MR_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    ///Bit 10 - Event Mask on line 10
127    #[inline(always)]
128    pub fn mr10(&self) -> MR_R {
129        MR_R::new(((self.bits >> 10) & 1) != 0)
130    }
131    ///Bit 11 - Event Mask on line 11
132    #[inline(always)]
133    pub fn mr11(&self) -> MR_R {
134        MR_R::new(((self.bits >> 11) & 1) != 0)
135    }
136    ///Bit 12 - Event Mask on line 12
137    #[inline(always)]
138    pub fn mr12(&self) -> MR_R {
139        MR_R::new(((self.bits >> 12) & 1) != 0)
140    }
141    ///Bit 13 - Event Mask on line 13
142    #[inline(always)]
143    pub fn mr13(&self) -> MR_R {
144        MR_R::new(((self.bits >> 13) & 1) != 0)
145    }
146    ///Bit 14 - Event Mask on line 14
147    #[inline(always)]
148    pub fn mr14(&self) -> MR_R {
149        MR_R::new(((self.bits >> 14) & 1) != 0)
150    }
151    ///Bit 15 - Event Mask on line 15
152    #[inline(always)]
153    pub fn mr15(&self) -> MR_R {
154        MR_R::new(((self.bits >> 15) & 1) != 0)
155    }
156    ///Bit 16 - Event Mask on line 16
157    #[inline(always)]
158    pub fn mr16(&self) -> MR_R {
159        MR_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    ///Bit 17 - Event Mask on line 17
162    #[inline(always)]
163    pub fn mr17(&self) -> MR_R {
164        MR_R::new(((self.bits >> 17) & 1) != 0)
165    }
166}
167impl core::fmt::Debug for R {
168    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
169        f.debug_struct("EMR")
170            .field("mr0", &self.mr0())
171            .field("mr1", &self.mr1())
172            .field("mr2", &self.mr2())
173            .field("mr3", &self.mr3())
174            .field("mr4", &self.mr4())
175            .field("mr5", &self.mr5())
176            .field("mr6", &self.mr6())
177            .field("mr7", &self.mr7())
178            .field("mr8", &self.mr8())
179            .field("mr9", &self.mr9())
180            .field("mr10", &self.mr10())
181            .field("mr11", &self.mr11())
182            .field("mr12", &self.mr12())
183            .field("mr13", &self.mr13())
184            .field("mr14", &self.mr14())
185            .field("mr15", &self.mr15())
186            .field("mr16", &self.mr16())
187            .field("mr17", &self.mr17())
188            .finish()
189    }
190}
191impl W {
192    ///Event Mask on line (0-17)
193    ///
194    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
195    #[inline(always)]
196    pub fn mr(&mut self, n: u8) -> MR_W<EMRrs> {
197        #[allow(clippy::no_effect)] [(); 18][n as usize];
198        MR_W::new(self, n)
199    }
200    ///Bit 0 - Event Mask on line 0
201    #[inline(always)]
202    pub fn mr0(&mut self) -> MR_W<EMRrs> {
203        MR_W::new(self, 0)
204    }
205    ///Bit 1 - Event Mask on line 1
206    #[inline(always)]
207    pub fn mr1(&mut self) -> MR_W<EMRrs> {
208        MR_W::new(self, 1)
209    }
210    ///Bit 2 - Event Mask on line 2
211    #[inline(always)]
212    pub fn mr2(&mut self) -> MR_W<EMRrs> {
213        MR_W::new(self, 2)
214    }
215    ///Bit 3 - Event Mask on line 3
216    #[inline(always)]
217    pub fn mr3(&mut self) -> MR_W<EMRrs> {
218        MR_W::new(self, 3)
219    }
220    ///Bit 4 - Event Mask on line 4
221    #[inline(always)]
222    pub fn mr4(&mut self) -> MR_W<EMRrs> {
223        MR_W::new(self, 4)
224    }
225    ///Bit 5 - Event Mask on line 5
226    #[inline(always)]
227    pub fn mr5(&mut self) -> MR_W<EMRrs> {
228        MR_W::new(self, 5)
229    }
230    ///Bit 6 - Event Mask on line 6
231    #[inline(always)]
232    pub fn mr6(&mut self) -> MR_W<EMRrs> {
233        MR_W::new(self, 6)
234    }
235    ///Bit 7 - Event Mask on line 7
236    #[inline(always)]
237    pub fn mr7(&mut self) -> MR_W<EMRrs> {
238        MR_W::new(self, 7)
239    }
240    ///Bit 8 - Event Mask on line 8
241    #[inline(always)]
242    pub fn mr8(&mut self) -> MR_W<EMRrs> {
243        MR_W::new(self, 8)
244    }
245    ///Bit 9 - Event Mask on line 9
246    #[inline(always)]
247    pub fn mr9(&mut self) -> MR_W<EMRrs> {
248        MR_W::new(self, 9)
249    }
250    ///Bit 10 - Event Mask on line 10
251    #[inline(always)]
252    pub fn mr10(&mut self) -> MR_W<EMRrs> {
253        MR_W::new(self, 10)
254    }
255    ///Bit 11 - Event Mask on line 11
256    #[inline(always)]
257    pub fn mr11(&mut self) -> MR_W<EMRrs> {
258        MR_W::new(self, 11)
259    }
260    ///Bit 12 - Event Mask on line 12
261    #[inline(always)]
262    pub fn mr12(&mut self) -> MR_W<EMRrs> {
263        MR_W::new(self, 12)
264    }
265    ///Bit 13 - Event Mask on line 13
266    #[inline(always)]
267    pub fn mr13(&mut self) -> MR_W<EMRrs> {
268        MR_W::new(self, 13)
269    }
270    ///Bit 14 - Event Mask on line 14
271    #[inline(always)]
272    pub fn mr14(&mut self) -> MR_W<EMRrs> {
273        MR_W::new(self, 14)
274    }
275    ///Bit 15 - Event Mask on line 15
276    #[inline(always)]
277    pub fn mr15(&mut self) -> MR_W<EMRrs> {
278        MR_W::new(self, 15)
279    }
280    ///Bit 16 - Event Mask on line 16
281    #[inline(always)]
282    pub fn mr16(&mut self) -> MR_W<EMRrs> {
283        MR_W::new(self, 16)
284    }
285    ///Bit 17 - Event Mask on line 17
286    #[inline(always)]
287    pub fn mr17(&mut self) -> MR_W<EMRrs> {
288        MR_W::new(self, 17)
289    }
290}
291/**Event mask register (EXTI_EMR)
292
293You can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
294
295See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#EXTI:EMR)*/
296pub struct EMRrs;
297impl crate::RegisterSpec for EMRrs {
298    type Ux = u32;
299}
300///`read()` method returns [`emr::R`](R) reader structure
301impl crate::Readable for EMRrs {}
302///`write(|w| ..)` method takes [`emr::W`](W) writer structure
303impl crate::Writable for EMRrs {
304    type Safety = crate::Unsafe;
305}
306///`reset()` method sets EMR to value 0
307impl crate::Resettable for EMRrs {}
stm32f1_staging/stm32f100/exti/emr.rs

stm32f1_staging/stm32f100/exti/
emr.rs
