stm32f1_staging/stm32f100/dbgmcu/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `DBG_SLEEP` reader - DBG_SLEEP
6pub type DBG_SLEEP_R = crate::BitReader;
7///Field `DBG_SLEEP` writer - DBG_SLEEP
8pub type DBG_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DBG_STOP` reader - DBG_STOP
10pub type DBG_STOP_R = crate::BitReader;
11///Field `DBG_STOP` writer - DBG_STOP
12pub type DBG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DBG_STANDBY` reader - DBG_STANDBY
14pub type DBG_STANDBY_R = crate::BitReader;
15///Field `DBG_STANDBY` writer - DBG_STANDBY
16pub type DBG_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `TRACE_IOEN` reader - TRACE_IOEN
18pub type TRACE_IOEN_R = crate::BitReader;
19///Field `TRACE_IOEN` writer - TRACE_IOEN
20pub type TRACE_IOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TRACE_MODE` reader - TRACE_MODE
22pub type TRACE_MODE_R = crate::FieldReader;
23///Field `TRACE_MODE` writer - TRACE_MODE
24pub type TRACE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `DBG_IWDG_STOP` reader - DBG_IWDG_STOP
26pub type DBG_IWDG_STOP_R = crate::BitReader;
27///Field `DBG_IWDG_STOP` writer - DBG_IWDG_STOP
28pub type DBG_IWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP
30pub type DBG_WWDG_STOP_R = crate::BitReader;
31///Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP
32pub type DBG_WWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `DBG_TIM1_STOP` reader - DBG_TIM1_STOP
34pub type DBG_TIM1_STOP_R = crate::BitReader;
35///Field `DBG_TIM1_STOP` writer - DBG_TIM1_STOP
36pub type DBG_TIM1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP
38pub type DBG_TIM2_STOP_R = crate::BitReader;
39///Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP
40pub type DBG_TIM2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DBG_TIM3_STOP` reader - DBG_TIM3_STOP
42pub type DBG_TIM3_STOP_R = crate::BitReader;
43///Field `DBG_TIM3_STOP` writer - DBG_TIM3_STOP
44pub type DBG_TIM3_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP
46pub type DBG_TIM4_STOP_R = crate::BitReader;
47///Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP
48pub type DBG_TIM4_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `DBG_I2C1_SMBUS_TIMEOUT` reader - DBG_I2C1_SMBUS_TIMEOUT
50pub type DBG_I2C1_SMBUS_TIMEOUT_R = crate::BitReader;
51///Field `DBG_I2C1_SMBUS_TIMEOUT` writer - DBG_I2C1_SMBUS_TIMEOUT
52pub type DBG_I2C1_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT
54pub type DBG_I2C2_SMBUS_TIMEOUT_R = crate::BitReader;
55///Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT
56pub type DBG_I2C2_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP
58pub type DBG_TIM5_STOP_R = crate::BitReader;
59///Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP
60pub type DBG_TIM5_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP
62pub type DBG_TIM6_STOP_R = crate::BitReader;
63///Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP
64pub type DBG_TIM6_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP
66pub type DBG_TIM7_STOP_R = crate::BitReader;
67///Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP
68pub type DBG_TIM7_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `DBG_TIM15_STOP` reader - DBG_TIM15_STOP
70pub type DBG_TIM15_STOP_R = crate::BitReader;
71///Field `DBG_TIM15_STOP` writer - DBG_TIM15_STOP
72pub type DBG_TIM15_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
73///Field `DBG_TIM16_STOP` reader - DBG_TIM16_STOP
74pub type DBG_TIM16_STOP_R = crate::BitReader;
75///Field `DBG_TIM16_STOP` writer - DBG_TIM16_STOP
76pub type DBG_TIM16_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
77///Field `DBG_TIM17_STOP` reader - DBG_TIM17_STOP
78pub type DBG_TIM17_STOP_R = crate::BitReader;
79///Field `DBG_TIM17_STOP` writer - DBG_TIM17_STOP
80pub type DBG_TIM17_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
81///Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP
82pub type DBG_TIM12_STOP_R = crate::BitReader;
83///Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP
84pub type DBG_TIM12_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
85///Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP
86pub type DBG_TIM13_STOP_R = crate::BitReader;
87///Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP
88pub type DBG_TIM13_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
89///Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP
90pub type DBG_TIM14_STOP_R = crate::BitReader;
91///Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP
92pub type DBG_TIM14_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
93impl R {
94    ///Bit 0 - DBG_SLEEP
95    #[inline(always)]
96    pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
97        DBG_SLEEP_R::new((self.bits & 1) != 0)
98    }
99    ///Bit 1 - DBG_STOP
100    #[inline(always)]
101    pub fn dbg_stop(&self) -> DBG_STOP_R {
102        DBG_STOP_R::new(((self.bits >> 1) & 1) != 0)
103    }
104    ///Bit 2 - DBG_STANDBY
105    #[inline(always)]
106    pub fn dbg_standby(&self) -> DBG_STANDBY_R {
107        DBG_STANDBY_R::new(((self.bits >> 2) & 1) != 0)
108    }
109    ///Bit 5 - TRACE_IOEN
110    #[inline(always)]
111    pub fn trace_ioen(&self) -> TRACE_IOEN_R {
112        TRACE_IOEN_R::new(((self.bits >> 5) & 1) != 0)
113    }
114    ///Bits 6:7 - TRACE_MODE
115    #[inline(always)]
116    pub fn trace_mode(&self) -> TRACE_MODE_R {
117        TRACE_MODE_R::new(((self.bits >> 6) & 3) as u8)
118    }
119    ///Bit 8 - DBG_IWDG_STOP
120    #[inline(always)]
121    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
122        DBG_IWDG_STOP_R::new(((self.bits >> 8) & 1) != 0)
123    }
124    ///Bit 9 - DBG_WWDG_STOP
125    #[inline(always)]
126    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
127        DBG_WWDG_STOP_R::new(((self.bits >> 9) & 1) != 0)
128    }
129    ///Bit 10 - DBG_TIM1_STOP
130    #[inline(always)]
131    pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R {
132        DBG_TIM1_STOP_R::new(((self.bits >> 10) & 1) != 0)
133    }
134    ///Bit 11 - DBG_TIM2_STOP
135    #[inline(always)]
136    pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R {
137        DBG_TIM2_STOP_R::new(((self.bits >> 11) & 1) != 0)
138    }
139    ///Bit 12 - DBG_TIM3_STOP
140    #[inline(always)]
141    pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R {
142        DBG_TIM3_STOP_R::new(((self.bits >> 12) & 1) != 0)
143    }
144    ///Bit 13 - DBG_TIM4_STOP
145    #[inline(always)]
146    pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R {
147        DBG_TIM4_STOP_R::new(((self.bits >> 13) & 1) != 0)
148    }
149    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
150    #[inline(always)]
151    pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R {
152        DBG_I2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 15) & 1) != 0)
153    }
154    ///Bit 16 - DBG_I2C2_SMBUS_TIMEOUT
155    #[inline(always)]
156    pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R {
157        DBG_I2C2_SMBUS_TIMEOUT_R::new(((self.bits >> 16) & 1) != 0)
158    }
159    ///Bit 18 - DBG_TIM5_STOP
160    #[inline(always)]
161    pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R {
162        DBG_TIM5_STOP_R::new(((self.bits >> 18) & 1) != 0)
163    }
164    ///Bit 19 - DBG_TIM6_STOP
165    #[inline(always)]
166    pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R {
167        DBG_TIM6_STOP_R::new(((self.bits >> 19) & 1) != 0)
168    }
169    ///Bit 20 - DBG_TIM7_STOP
170    #[inline(always)]
171    pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R {
172        DBG_TIM7_STOP_R::new(((self.bits >> 20) & 1) != 0)
173    }
174    ///Bit 22 - DBG_TIM15_STOP
175    #[inline(always)]
176    pub fn dbg_tim15_stop(&self) -> DBG_TIM15_STOP_R {
177        DBG_TIM15_STOP_R::new(((self.bits >> 22) & 1) != 0)
178    }
179    ///Bit 23 - DBG_TIM16_STOP
180    #[inline(always)]
181    pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R {
182        DBG_TIM16_STOP_R::new(((self.bits >> 23) & 1) != 0)
183    }
184    ///Bit 24 - DBG_TIM17_STOP
185    #[inline(always)]
186    pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R {
187        DBG_TIM17_STOP_R::new(((self.bits >> 24) & 1) != 0)
188    }
189    ///Bit 25 - DBG_TIM12_STOP
190    #[inline(always)]
191    pub fn dbg_tim12_stop(&self) -> DBG_TIM12_STOP_R {
192        DBG_TIM12_STOP_R::new(((self.bits >> 25) & 1) != 0)
193    }
194    ///Bit 26 - DBG_TIM13_STOP
195    #[inline(always)]
196    pub fn dbg_tim13_stop(&self) -> DBG_TIM13_STOP_R {
197        DBG_TIM13_STOP_R::new(((self.bits >> 26) & 1) != 0)
198    }
199    ///Bit 27 - DBG_TIM14_STOP
200    #[inline(always)]
201    pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R {
202        DBG_TIM14_STOP_R::new(((self.bits >> 27) & 1) != 0)
203    }
204}
205impl core::fmt::Debug for R {
206    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
207        f.debug_struct("CR")
208            .field("dbg_sleep", &self.dbg_sleep())
209            .field("dbg_stop", &self.dbg_stop())
210            .field("dbg_standby", &self.dbg_standby())
211            .field("trace_ioen", &self.trace_ioen())
212            .field("trace_mode", &self.trace_mode())
213            .field("dbg_iwdg_stop", &self.dbg_iwdg_stop())
214            .field("dbg_wwdg_stop", &self.dbg_wwdg_stop())
215            .field("dbg_tim1_stop", &self.dbg_tim1_stop())
216            .field("dbg_tim2_stop", &self.dbg_tim2_stop())
217            .field("dbg_tim3_stop", &self.dbg_tim3_stop())
218            .field("dbg_tim4_stop", &self.dbg_tim4_stop())
219            .field("dbg_i2c1_smbus_timeout", &self.dbg_i2c1_smbus_timeout())
220            .field("dbg_i2c2_smbus_timeout", &self.dbg_i2c2_smbus_timeout())
221            .field("dbg_tim5_stop", &self.dbg_tim5_stop())
222            .field("dbg_tim6_stop", &self.dbg_tim6_stop())
223            .field("dbg_tim7_stop", &self.dbg_tim7_stop())
224            .field("dbg_tim15_stop", &self.dbg_tim15_stop())
225            .field("dbg_tim16_stop", &self.dbg_tim16_stop())
226            .field("dbg_tim17_stop", &self.dbg_tim17_stop())
227            .field("dbg_tim12_stop", &self.dbg_tim12_stop())
228            .field("dbg_tim13_stop", &self.dbg_tim13_stop())
229            .field("dbg_tim14_stop", &self.dbg_tim14_stop())
230            .finish()
231    }
232}
233impl W {
234    ///Bit 0 - DBG_SLEEP
235    #[inline(always)]
236    pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<CRrs> {
237        DBG_SLEEP_W::new(self, 0)
238    }
239    ///Bit 1 - DBG_STOP
240    #[inline(always)]
241    pub fn dbg_stop(&mut self) -> DBG_STOP_W<CRrs> {
242        DBG_STOP_W::new(self, 1)
243    }
244    ///Bit 2 - DBG_STANDBY
245    #[inline(always)]
246    pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<CRrs> {
247        DBG_STANDBY_W::new(self, 2)
248    }
249    ///Bit 5 - TRACE_IOEN
250    #[inline(always)]
251    pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<CRrs> {
252        TRACE_IOEN_W::new(self, 5)
253    }
254    ///Bits 6:7 - TRACE_MODE
255    #[inline(always)]
256    pub fn trace_mode(&mut self) -> TRACE_MODE_W<CRrs> {
257        TRACE_MODE_W::new(self, 6)
258    }
259    ///Bit 8 - DBG_IWDG_STOP
260    #[inline(always)]
261    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<CRrs> {
262        DBG_IWDG_STOP_W::new(self, 8)
263    }
264    ///Bit 9 - DBG_WWDG_STOP
265    #[inline(always)]
266    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<CRrs> {
267        DBG_WWDG_STOP_W::new(self, 9)
268    }
269    ///Bit 10 - DBG_TIM1_STOP
270    #[inline(always)]
271    pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<CRrs> {
272        DBG_TIM1_STOP_W::new(self, 10)
273    }
274    ///Bit 11 - DBG_TIM2_STOP
275    #[inline(always)]
276    pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<CRrs> {
277        DBG_TIM2_STOP_W::new(self, 11)
278    }
279    ///Bit 12 - DBG_TIM3_STOP
280    #[inline(always)]
281    pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<CRrs> {
282        DBG_TIM3_STOP_W::new(self, 12)
283    }
284    ///Bit 13 - DBG_TIM4_STOP
285    #[inline(always)]
286    pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<CRrs> {
287        DBG_TIM4_STOP_W::new(self, 13)
288    }
289    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
290    #[inline(always)]
291    pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<CRrs> {
292        DBG_I2C1_SMBUS_TIMEOUT_W::new(self, 15)
293    }
294    ///Bit 16 - DBG_I2C2_SMBUS_TIMEOUT
295    #[inline(always)]
296    pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<CRrs> {
297        DBG_I2C2_SMBUS_TIMEOUT_W::new(self, 16)
298    }
299    ///Bit 18 - DBG_TIM5_STOP
300    #[inline(always)]
301    pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<CRrs> {
302        DBG_TIM5_STOP_W::new(self, 18)
303    }
304    ///Bit 19 - DBG_TIM6_STOP
305    #[inline(always)]
306    pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<CRrs> {
307        DBG_TIM6_STOP_W::new(self, 19)
308    }
309    ///Bit 20 - DBG_TIM7_STOP
310    #[inline(always)]
311    pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<CRrs> {
312        DBG_TIM7_STOP_W::new(self, 20)
313    }
314    ///Bit 22 - DBG_TIM15_STOP
315    #[inline(always)]
316    pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<CRrs> {
317        DBG_TIM15_STOP_W::new(self, 22)
318    }
319    ///Bit 23 - DBG_TIM16_STOP
320    #[inline(always)]
321    pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<CRrs> {
322        DBG_TIM16_STOP_W::new(self, 23)
323    }
324    ///Bit 24 - DBG_TIM17_STOP
325    #[inline(always)]
326    pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<CRrs> {
327        DBG_TIM17_STOP_W::new(self, 24)
328    }
329    ///Bit 25 - DBG_TIM12_STOP
330    #[inline(always)]
331    pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<CRrs> {
332        DBG_TIM12_STOP_W::new(self, 25)
333    }
334    ///Bit 26 - DBG_TIM13_STOP
335    #[inline(always)]
336    pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<CRrs> {
337        DBG_TIM13_STOP_W::new(self, 26)
338    }
339    ///Bit 27 - DBG_TIM14_STOP
340    #[inline(always)]
341    pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<CRrs> {
342        DBG_TIM14_STOP_W::new(self, 27)
343    }
344}
345/**DBGMCU_CR
346
347You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
348
349See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DBGMCU:CR)*/
350pub struct CRrs;
351impl crate::RegisterSpec for CRrs {
352    type Ux = u32;
353}
354///`read()` method returns [`cr::R`](R) reader structure
355impl crate::Readable for CRrs {}
356///`write(|w| ..)` method takes [`cr::W`](W) writer structure
357impl crate::Writable for CRrs {
358    type Safety = crate::Unsafe;
359}
360///`reset()` method sets CR to value 0
361impl crate::Resettable for CRrs {}
stm32f1_staging/stm32f100/dbgmcu/cr.rs

stm32f1_staging/stm32f100/dbgmcu/
cr.rs
