stm32f1_staging/stm32f100/dac/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**DAC channel1 DMA underrun flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DMAUDR1 {
11    ///0: No DMA underrun error condition occurred for DAC channel X
12    NoUnderrun = 0,
13    ///1: DMA underrun error condition occurred for DAC channel X
14    Underrun = 1,
15}
16impl From<DMAUDR1> for bool {
17    #[inline(always)]
18    fn from(variant: DMAUDR1) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DMAUDR1` reader - DAC channel1 DMA underrun flag
23pub type DMAUDR1_R = crate::BitReader<DMAUDR1>;
24impl DMAUDR1_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DMAUDR1 {
28        match self.bits {
29            false => DMAUDR1::NoUnderrun,
30            true => DMAUDR1::Underrun,
31        }
32    }
33    ///No DMA underrun error condition occurred for DAC channel X
34    #[inline(always)]
35    pub fn is_no_underrun(&self) -> bool {
36        *self == DMAUDR1::NoUnderrun
37    }
38    ///DMA underrun error condition occurred for DAC channel X
39    #[inline(always)]
40    pub fn is_underrun(&self) -> bool {
41        *self == DMAUDR1::Underrun
42    }
43}
44///Field `DMAUDR1` writer - DAC channel1 DMA underrun flag
45pub type DMAUDR1_W<'a, REG> = crate::BitWriter<'a, REG, DMAUDR1>;
46impl<'a, REG> DMAUDR1_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///No DMA underrun error condition occurred for DAC channel X
51    #[inline(always)]
52    pub fn no_underrun(self) -> &'a mut crate::W<REG> {
53        self.variant(DMAUDR1::NoUnderrun)
54    }
55    ///DMA underrun error condition occurred for DAC channel X
56    #[inline(always)]
57    pub fn underrun(self) -> &'a mut crate::W<REG> {
58        self.variant(DMAUDR1::Underrun)
59    }
60}
61///Field `DMAUDR2` reader - DAC channel2 DMA underrun flag
62pub use DMAUDR1_R as DMAUDR2_R;
63///Field `DMAUDR2` writer - DAC channel2 DMA underrun flag
64pub use DMAUDR1_W as DMAUDR2_W;
65impl R {
66    ///Bit 13 - DAC channel1 DMA underrun flag
67    #[inline(always)]
68    pub fn dmaudr1(&self) -> DMAUDR1_R {
69        DMAUDR1_R::new(((self.bits >> 13) & 1) != 0)
70    }
71    ///Bit 29 - DAC channel2 DMA underrun flag
72    #[inline(always)]
73    pub fn dmaudr2(&self) -> DMAUDR2_R {
74        DMAUDR2_R::new(((self.bits >> 29) & 1) != 0)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("SR")
80            .field("dmaudr1", &self.dmaudr1())
81            .field("dmaudr2", &self.dmaudr2())
82            .finish()
83    }
84}
85impl W {
86    ///Bit 13 - DAC channel1 DMA underrun flag
87    #[inline(always)]
88    pub fn dmaudr1(&mut self) -> DMAUDR1_W<SRrs> {
89        DMAUDR1_W::new(self, 13)
90    }
91    ///Bit 29 - DAC channel2 DMA underrun flag
92    #[inline(always)]
93    pub fn dmaudr2(&mut self) -> DMAUDR2_W<SRrs> {
94        DMAUDR2_W::new(self, 29)
95    }
96}
97/**DAC status register
98
99You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:SR)*/
102pub struct SRrs;
103impl crate::RegisterSpec for SRrs {
104    type Ux = u32;
105}
106///`read()` method returns [`sr::R`](R) reader structure
107impl crate::Readable for SRrs {}
108///`write(|w| ..)` method takes [`sr::W`](W) writer structure
109impl crate::Writable for SRrs {
110    type Safety = crate::Unsafe;
111}
112///`reset()` method sets SR to value 0
113impl crate::Resettable for SRrs {}
stm32f1_staging/stm32f100/dac/sr.rs

stm32f1_staging/stm32f100/dac/
sr.rs
