stm32f1_staging/stm32f100/cec/
cfgr.rs

1///Register `CFGR` reader
2pub type R = crate::R<CFGRrs>;
3///Register `CFGR` writer
4pub type W = crate::W<CFGRrs>;
5///Field `PE` reader - Peripheral enable
6pub type PE_R = crate::BitReader;
7///Field `PE` writer - Peripheral enable
8pub type PE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `IE` reader - Interrupt enable
10pub type IE_R = crate::BitReader;
11///Field `IE` writer - Interrupt enable
12pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `BTEM` reader - Bit timing error mode
14pub type BTEM_R = crate::BitReader;
15///Field `BTEM` writer - Bit timing error mode
16pub type BTEM_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `BPEM` reader - Bit period error mode
18pub type BPEM_R = crate::BitReader;
19///Field `BPEM` writer - Bit period error mode
20pub type BPEM_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    ///Bit 0 - Peripheral enable
23    #[inline(always)]
24    pub fn pe(&self) -> PE_R {
25        PE_R::new((self.bits & 1) != 0)
26    }
27    ///Bit 1 - Interrupt enable
28    #[inline(always)]
29    pub fn ie(&self) -> IE_R {
30        IE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    ///Bit 2 - Bit timing error mode
33    #[inline(always)]
34    pub fn btem(&self) -> BTEM_R {
35        BTEM_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    ///Bit 3 - Bit period error mode
38    #[inline(always)]
39    pub fn bpem(&self) -> BPEM_R {
40        BPEM_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("CFGR")
46            .field("pe", &self.pe())
47            .field("ie", &self.ie())
48            .field("btem", &self.btem())
49            .field("bpem", &self.bpem())
50            .finish()
51    }
52}
53impl W {
54    ///Bit 0 - Peripheral enable
55    #[inline(always)]
56    pub fn pe(&mut self) -> PE_W<CFGRrs> {
57        PE_W::new(self, 0)
58    }
59    ///Bit 1 - Interrupt enable
60    #[inline(always)]
61    pub fn ie(&mut self) -> IE_W<CFGRrs> {
62        IE_W::new(self, 1)
63    }
64    ///Bit 2 - Bit timing error mode
65    #[inline(always)]
66    pub fn btem(&mut self) -> BTEM_W<CFGRrs> {
67        BTEM_W::new(self, 2)
68    }
69    ///Bit 3 - Bit period error mode
70    #[inline(always)]
71    pub fn bpem(&mut self) -> BPEM_W<CFGRrs> {
72        BPEM_W::new(self, 3)
73    }
74}
75/**configuration register
76
77You can [`read`](crate::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#CEC:CFGR)*/
80pub struct CFGRrs;
81impl crate::RegisterSpec for CFGRrs {
82    type Ux = u32;
83}
84///`read()` method returns [`cfgr::R`](R) reader structure
85impl crate::Readable for CFGRrs {}
86///`write(|w| ..)` method takes [`cfgr::W`](W) writer structure
87impl crate::Writable for CFGRrs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets CFGR to value 0
91impl crate::Resettable for CFGRrs {}
stm32f1_staging/stm32f100/cec/cfgr.rs

stm32f1_staging/stm32f100/cec/
cfgr.rs
