stm32f1_staging/stm32f100/afio/
mapr2.rs

1///Register `MAPR2` reader
2pub type R = crate::R<MAPR2rs>;
3///Register `MAPR2` writer
4pub type W = crate::W<MAPR2rs>;
5///Field `TIM15_REMAP` reader - TIM15 remapping
6pub type TIM15_REMAP_R = crate::BitReader;
7///Field `TIM15_REMAP` writer - TIM15 remapping
8pub type TIM15_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `TIM16_REMAP` reader - TIM16 remapping
10pub type TIM16_REMAP_R = crate::BitReader;
11///Field `TIM16_REMAP` writer - TIM16 remapping
12pub type TIM16_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TIM17_REMAP` reader - TIM17 remapping
14pub type TIM17_REMAP_R = crate::BitReader;
15///Field `TIM17_REMAP` writer - TIM17 remapping
16pub type TIM17_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CEC_REMAP` reader - CEC remapping
18pub type CEC_REMAP_R = crate::BitReader;
19///Field `CEC_REMAP` writer - CEC remapping
20pub type CEC_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TIM1_DMA_REMAP` reader - TIM1 DMA remapping
22pub type TIM1_DMA_REMAP_R = crate::BitReader;
23///Field `TIM1_DMA_REMAP` writer - TIM1 DMA remapping
24pub type TIM1_DMA_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `TIM13_REMAP` reader - TIM13 remapping
26pub type TIM13_REMAP_R = crate::BitReader;
27///Field `TIM13_REMAP` writer - TIM13 remapping
28pub type TIM13_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `TIM14_REMAP` reader - TIM14 remapping
30pub type TIM14_REMAP_R = crate::BitReader;
31///Field `TIM14_REMAP` writer - TIM14 remapping
32pub type TIM14_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `FSMC_NADV` reader - NADV connect/disconnect
34pub type FSMC_NADV_R = crate::BitReader;
35///Field `FSMC_NADV` writer - NADV connect/disconnect
36pub type FSMC_NADV_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `TIM67_DAC_DMA_REMAP` reader - TIM67_DAC DMA remapping
38pub type TIM67_DAC_DMA_REMAP_R = crate::BitReader;
39///Field `TIM67_DAC_DMA_REMAP` writer - TIM67_DAC DMA remapping
40pub type TIM67_DAC_DMA_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `TIM12_REMAP` reader - TIM12 remapping
42pub type TIM12_REMAP_R = crate::BitReader;
43///Field `TIM12_REMAP` writer - TIM12 remapping
44pub type TIM12_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `MISC_REMAP` reader - Miscellaneous features remapping
46pub type MISC_REMAP_R = crate::BitReader;
47///Field `MISC_REMAP` writer - Miscellaneous features remapping
48pub type MISC_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    ///Bit 0 - TIM15 remapping
51    #[inline(always)]
52    pub fn tim15_remap(&self) -> TIM15_REMAP_R {
53        TIM15_REMAP_R::new((self.bits & 1) != 0)
54    }
55    ///Bit 1 - TIM16 remapping
56    #[inline(always)]
57    pub fn tim16_remap(&self) -> TIM16_REMAP_R {
58        TIM16_REMAP_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    ///Bit 2 - TIM17 remapping
61    #[inline(always)]
62    pub fn tim17_remap(&self) -> TIM17_REMAP_R {
63        TIM17_REMAP_R::new(((self.bits >> 2) & 1) != 0)
64    }
65    ///Bit 3 - CEC remapping
66    #[inline(always)]
67    pub fn cec_remap(&self) -> CEC_REMAP_R {
68        CEC_REMAP_R::new(((self.bits >> 3) & 1) != 0)
69    }
70    ///Bit 4 - TIM1 DMA remapping
71    #[inline(always)]
72    pub fn tim1_dma_remap(&self) -> TIM1_DMA_REMAP_R {
73        TIM1_DMA_REMAP_R::new(((self.bits >> 4) & 1) != 0)
74    }
75    ///Bit 8 - TIM13 remapping
76    #[inline(always)]
77    pub fn tim13_remap(&self) -> TIM13_REMAP_R {
78        TIM13_REMAP_R::new(((self.bits >> 8) & 1) != 0)
79    }
80    ///Bit 9 - TIM14 remapping
81    #[inline(always)]
82    pub fn tim14_remap(&self) -> TIM14_REMAP_R {
83        TIM14_REMAP_R::new(((self.bits >> 9) & 1) != 0)
84    }
85    ///Bit 10 - NADV connect/disconnect
86    #[inline(always)]
87    pub fn fsmc_nadv(&self) -> FSMC_NADV_R {
88        FSMC_NADV_R::new(((self.bits >> 10) & 1) != 0)
89    }
90    ///Bit 11 - TIM67_DAC DMA remapping
91    #[inline(always)]
92    pub fn tim67_dac_dma_remap(&self) -> TIM67_DAC_DMA_REMAP_R {
93        TIM67_DAC_DMA_REMAP_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    ///Bit 12 - TIM12 remapping
96    #[inline(always)]
97    pub fn tim12_remap(&self) -> TIM12_REMAP_R {
98        TIM12_REMAP_R::new(((self.bits >> 12) & 1) != 0)
99    }
100    ///Bit 13 - Miscellaneous features remapping
101    #[inline(always)]
102    pub fn misc_remap(&self) -> MISC_REMAP_R {
103        MISC_REMAP_R::new(((self.bits >> 13) & 1) != 0)
104    }
105}
106impl core::fmt::Debug for R {
107    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
108        f.debug_struct("MAPR2")
109            .field("tim15_remap", &self.tim15_remap())
110            .field("tim16_remap", &self.tim16_remap())
111            .field("tim17_remap", &self.tim17_remap())
112            .field("tim13_remap", &self.tim13_remap())
113            .field("tim14_remap", &self.tim14_remap())
114            .field("fsmc_nadv", &self.fsmc_nadv())
115            .field("cec_remap", &self.cec_remap())
116            .field("tim1_dma_remap", &self.tim1_dma_remap())
117            .field("tim67_dac_dma_remap", &self.tim67_dac_dma_remap())
118            .field("tim12_remap", &self.tim12_remap())
119            .field("misc_remap", &self.misc_remap())
120            .finish()
121    }
122}
123impl W {
124    ///Bit 0 - TIM15 remapping
125    #[inline(always)]
126    pub fn tim15_remap(&mut self) -> TIM15_REMAP_W<MAPR2rs> {
127        TIM15_REMAP_W::new(self, 0)
128    }
129    ///Bit 1 - TIM16 remapping
130    #[inline(always)]
131    pub fn tim16_remap(&mut self) -> TIM16_REMAP_W<MAPR2rs> {
132        TIM16_REMAP_W::new(self, 1)
133    }
134    ///Bit 2 - TIM17 remapping
135    #[inline(always)]
136    pub fn tim17_remap(&mut self) -> TIM17_REMAP_W<MAPR2rs> {
137        TIM17_REMAP_W::new(self, 2)
138    }
139    ///Bit 3 - CEC remapping
140    #[inline(always)]
141    pub fn cec_remap(&mut self) -> CEC_REMAP_W<MAPR2rs> {
142        CEC_REMAP_W::new(self, 3)
143    }
144    ///Bit 4 - TIM1 DMA remapping
145    #[inline(always)]
146    pub fn tim1_dma_remap(&mut self) -> TIM1_DMA_REMAP_W<MAPR2rs> {
147        TIM1_DMA_REMAP_W::new(self, 4)
148    }
149    ///Bit 8 - TIM13 remapping
150    #[inline(always)]
151    pub fn tim13_remap(&mut self) -> TIM13_REMAP_W<MAPR2rs> {
152        TIM13_REMAP_W::new(self, 8)
153    }
154    ///Bit 9 - TIM14 remapping
155    #[inline(always)]
156    pub fn tim14_remap(&mut self) -> TIM14_REMAP_W<MAPR2rs> {
157        TIM14_REMAP_W::new(self, 9)
158    }
159    ///Bit 10 - NADV connect/disconnect
160    #[inline(always)]
161    pub fn fsmc_nadv(&mut self) -> FSMC_NADV_W<MAPR2rs> {
162        FSMC_NADV_W::new(self, 10)
163    }
164    ///Bit 11 - TIM67_DAC DMA remapping
165    #[inline(always)]
166    pub fn tim67_dac_dma_remap(&mut self) -> TIM67_DAC_DMA_REMAP_W<MAPR2rs> {
167        TIM67_DAC_DMA_REMAP_W::new(self, 11)
168    }
169    ///Bit 12 - TIM12 remapping
170    #[inline(always)]
171    pub fn tim12_remap(&mut self) -> TIM12_REMAP_W<MAPR2rs> {
172        TIM12_REMAP_W::new(self, 12)
173    }
174    ///Bit 13 - Miscellaneous features remapping
175    #[inline(always)]
176    pub fn misc_remap(&mut self) -> MISC_REMAP_W<MAPR2rs> {
177        MISC_REMAP_W::new(self, 13)
178    }
179}
180/**AF remap and debug I/O configuration register
181
182You can [`read`](crate::Reg::read) this register and get [`mapr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mapr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#AFIO:MAPR2)*/
185pub struct MAPR2rs;
186impl crate::RegisterSpec for MAPR2rs {
187    type Ux = u32;
188}
189///`read()` method returns [`mapr2::R`](R) reader structure
190impl crate::Readable for MAPR2rs {}
191///`write(|w| ..)` method takes [`mapr2::W`](W) writer structure
192impl crate::Writable for MAPR2rs {
193    type Safety = crate::Unsafe;
194}
195///`reset()` method sets MAPR2 to value 0
196impl crate::Resettable for MAPR2rs {}
stm32f1_staging/stm32f100/afio/mapr2.rs

stm32f1_staging/stm32f100/afio/
mapr2.rs
