stm32f1_staging/stm32f100/afio/
mapr.rs

1///Register `MAPR` reader
2pub type R = crate::R<MAPRrs>;
3///Register `MAPR` writer
4pub type W = crate::W<MAPRrs>;
5///Field `SPI1_REMAP` reader - SPI1 remapping
6pub type SPI1_REMAP_R = crate::BitReader;
7///Field `SPI1_REMAP` writer - SPI1 remapping
8pub type SPI1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `I2C1_REMAP` reader - I2C1 remapping
10pub type I2C1_REMAP_R = crate::BitReader;
11///Field `I2C1_REMAP` writer - I2C1 remapping
12pub type I2C1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `USART1_REMAP` reader - USART1 remapping
14pub type USART1_REMAP_R = crate::BitReader;
15///Field `USART1_REMAP` writer - USART1 remapping
16pub type USART1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `USART2_REMAP` reader - USART2 remapping
18pub type USART2_REMAP_R = crate::BitReader;
19///Field `USART2_REMAP` writer - USART2 remapping
20pub type USART2_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `USART3_REMAP` reader - USART3 remapping
22pub type USART3_REMAP_R = crate::FieldReader;
23///Field `USART3_REMAP` writer - USART3 remapping
24pub type USART3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `TIM1_REMAP` reader - TIM1 remapping
26pub type TIM1_REMAP_R = crate::FieldReader;
27///Field `TIM1_REMAP` writer - TIM1 remapping
28pub type TIM1_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `TIM2_REMAP` reader - TIM2 remapping
30pub type TIM2_REMAP_R = crate::FieldReader;
31///Field `TIM2_REMAP` writer - TIM2 remapping
32pub type TIM2_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33///Field `TIM3_REMAP` reader - TIM3 remapping
34pub type TIM3_REMAP_R = crate::FieldReader;
35///Field `TIM3_REMAP` writer - TIM3 remapping
36pub type TIM3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37///Field `TIM4_REMAP` reader - TIM4 remapping
38pub type TIM4_REMAP_R = crate::BitReader;
39///Field `TIM4_REMAP` writer - TIM4 remapping
40pub type TIM4_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `PD01_REMAP` reader - Port D0/Port D1 mapping on OSCIN/OSCOUT
42pub type PD01_REMAP_R = crate::BitReader;
43///Field `PD01_REMAP` writer - Port D0/Port D1 mapping on OSCIN/OSCOUT
44pub type PD01_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `TIM5CH4_IREMAP` reader - Set and cleared by software
46pub type TIM5CH4_IREMAP_R = crate::BitReader;
47///Field `TIM5CH4_IREMAP` writer - Set and cleared by software
48pub type TIM5CH4_IREMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `SWJ_CFG` writer - Serial wire JTAG configuration
50pub type SWJ_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
51impl R {
52    ///Bit 0 - SPI1 remapping
53    #[inline(always)]
54    pub fn spi1_remap(&self) -> SPI1_REMAP_R {
55        SPI1_REMAP_R::new((self.bits & 1) != 0)
56    }
57    ///Bit 1 - I2C1 remapping
58    #[inline(always)]
59    pub fn i2c1_remap(&self) -> I2C1_REMAP_R {
60        I2C1_REMAP_R::new(((self.bits >> 1) & 1) != 0)
61    }
62    ///Bit 2 - USART1 remapping
63    #[inline(always)]
64    pub fn usart1_remap(&self) -> USART1_REMAP_R {
65        USART1_REMAP_R::new(((self.bits >> 2) & 1) != 0)
66    }
67    ///Bit 3 - USART2 remapping
68    #[inline(always)]
69    pub fn usart2_remap(&self) -> USART2_REMAP_R {
70        USART2_REMAP_R::new(((self.bits >> 3) & 1) != 0)
71    }
72    ///Bits 4:5 - USART3 remapping
73    #[inline(always)]
74    pub fn usart3_remap(&self) -> USART3_REMAP_R {
75        USART3_REMAP_R::new(((self.bits >> 4) & 3) as u8)
76    }
77    ///Bits 6:7 - TIM1 remapping
78    #[inline(always)]
79    pub fn tim1_remap(&self) -> TIM1_REMAP_R {
80        TIM1_REMAP_R::new(((self.bits >> 6) & 3) as u8)
81    }
82    ///Bits 8:9 - TIM2 remapping
83    #[inline(always)]
84    pub fn tim2_remap(&self) -> TIM2_REMAP_R {
85        TIM2_REMAP_R::new(((self.bits >> 8) & 3) as u8)
86    }
87    ///Bits 10:11 - TIM3 remapping
88    #[inline(always)]
89    pub fn tim3_remap(&self) -> TIM3_REMAP_R {
90        TIM3_REMAP_R::new(((self.bits >> 10) & 3) as u8)
91    }
92    ///Bit 12 - TIM4 remapping
93    #[inline(always)]
94    pub fn tim4_remap(&self) -> TIM4_REMAP_R {
95        TIM4_REMAP_R::new(((self.bits >> 12) & 1) != 0)
96    }
97    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
98    #[inline(always)]
99    pub fn pd01_remap(&self) -> PD01_REMAP_R {
100        PD01_REMAP_R::new(((self.bits >> 15) & 1) != 0)
101    }
102    ///Bit 16 - Set and cleared by software
103    #[inline(always)]
104    pub fn tim5ch4_iremap(&self) -> TIM5CH4_IREMAP_R {
105        TIM5CH4_IREMAP_R::new(((self.bits >> 16) & 1) != 0)
106    }
107}
108impl core::fmt::Debug for R {
109    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
110        f.debug_struct("MAPR")
111            .field("spi1_remap", &self.spi1_remap())
112            .field("i2c1_remap", &self.i2c1_remap())
113            .field("usart1_remap", &self.usart1_remap())
114            .field("usart2_remap", &self.usart2_remap())
115            .field("usart3_remap", &self.usart3_remap())
116            .field("tim1_remap", &self.tim1_remap())
117            .field("tim2_remap", &self.tim2_remap())
118            .field("tim3_remap", &self.tim3_remap())
119            .field("tim4_remap", &self.tim4_remap())
120            .field("pd01_remap", &self.pd01_remap())
121            .field("tim5ch4_iremap", &self.tim5ch4_iremap())
122            .finish()
123    }
124}
125impl W {
126    ///Bit 0 - SPI1 remapping
127    #[inline(always)]
128    pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<MAPRrs> {
129        SPI1_REMAP_W::new(self, 0)
130    }
131    ///Bit 1 - I2C1 remapping
132    #[inline(always)]
133    pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<MAPRrs> {
134        I2C1_REMAP_W::new(self, 1)
135    }
136    ///Bit 2 - USART1 remapping
137    #[inline(always)]
138    pub fn usart1_remap(&mut self) -> USART1_REMAP_W<MAPRrs> {
139        USART1_REMAP_W::new(self, 2)
140    }
141    ///Bit 3 - USART2 remapping
142    #[inline(always)]
143    pub fn usart2_remap(&mut self) -> USART2_REMAP_W<MAPRrs> {
144        USART2_REMAP_W::new(self, 3)
145    }
146    ///Bits 4:5 - USART3 remapping
147    #[inline(always)]
148    pub fn usart3_remap(&mut self) -> USART3_REMAP_W<MAPRrs> {
149        USART3_REMAP_W::new(self, 4)
150    }
151    ///Bits 6:7 - TIM1 remapping
152    #[inline(always)]
153    pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<MAPRrs> {
154        TIM1_REMAP_W::new(self, 6)
155    }
156    ///Bits 8:9 - TIM2 remapping
157    #[inline(always)]
158    pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<MAPRrs> {
159        TIM2_REMAP_W::new(self, 8)
160    }
161    ///Bits 10:11 - TIM3 remapping
162    #[inline(always)]
163    pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<MAPRrs> {
164        TIM3_REMAP_W::new(self, 10)
165    }
166    ///Bit 12 - TIM4 remapping
167    #[inline(always)]
168    pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<MAPRrs> {
169        TIM4_REMAP_W::new(self, 12)
170    }
171    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
172    #[inline(always)]
173    pub fn pd01_remap(&mut self) -> PD01_REMAP_W<MAPRrs> {
174        PD01_REMAP_W::new(self, 15)
175    }
176    ///Bit 16 - Set and cleared by software
177    #[inline(always)]
178    pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<MAPRrs> {
179        TIM5CH4_IREMAP_W::new(self, 16)
180    }
181    ///Bits 24:26 - Serial wire JTAG configuration
182    #[inline(always)]
183    pub fn swj_cfg(&mut self) -> SWJ_CFG_W<MAPRrs> {
184        SWJ_CFG_W::new(self, 24)
185    }
186}
187/**AF remap and debug I/O configuration register (AFIO_MAPR)
188
189You can [`read`](crate::Reg::read) this register and get [`mapr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mapr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#AFIO:MAPR)*/
192pub struct MAPRrs;
193impl crate::RegisterSpec for MAPRrs {
194    type Ux = u32;
195}
196///`read()` method returns [`mapr::R`](R) reader structure
197impl crate::Readable for MAPRrs {}
198///`write(|w| ..)` method takes [`mapr::W`](W) writer structure
199impl crate::Writable for MAPRrs {
200    type Safety = crate::Unsafe;
201}
202///`reset()` method sets MAPR to value 0
203impl crate::Resettable for MAPRrs {}
stm32f1_staging/stm32f100/afio/mapr.rs

stm32f1_staging/stm32f100/afio/
mapr.rs
