stm32f1_staging/stm32f100/adc1/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5///Field `AWDCH` reader - Analog watchdog channel select bits
6pub type AWDCH_R = crate::FieldReader;
7///Field `AWDCH` writer - Analog watchdog channel select bits
8pub type AWDCH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9/**Interrupt enable for EOC
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum EOCIE {
15    ///0: EOC interrupt disabled
16    Disabled = 0,
17    ///1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set
18    Enabled = 1,
19}
20impl From<EOCIE> for bool {
21    #[inline(always)]
22    fn from(variant: EOCIE) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `EOCIE` reader - Interrupt enable for EOC
27pub type EOCIE_R = crate::BitReader<EOCIE>;
28impl EOCIE_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> EOCIE {
32        match self.bits {
33            false => EOCIE::Disabled,
34            true => EOCIE::Enabled,
35        }
36    }
37    ///EOC interrupt disabled
38    #[inline(always)]
39    pub fn is_disabled(&self) -> bool {
40        *self == EOCIE::Disabled
41    }
42    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set
43    #[inline(always)]
44    pub fn is_enabled(&self) -> bool {
45        *self == EOCIE::Enabled
46    }
47}
48///Field `EOCIE` writer - Interrupt enable for EOC
49pub type EOCIE_W<'a, REG> = crate::BitWriter<'a, REG, EOCIE>;
50impl<'a, REG> EOCIE_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///EOC interrupt disabled
55    #[inline(always)]
56    pub fn disabled(self) -> &'a mut crate::W<REG> {
57        self.variant(EOCIE::Disabled)
58    }
59    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set
60    #[inline(always)]
61    pub fn enabled(self) -> &'a mut crate::W<REG> {
62        self.variant(EOCIE::Enabled)
63    }
64}
65/**Analog watchdog interrupt enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum AWDIE {
71    ///0: Analog watchdog interrupt disabled
72    Disabled = 0,
73    ///1: Analog watchdog interrupt enabled
74    Enabled = 1,
75}
76impl From<AWDIE> for bool {
77    #[inline(always)]
78    fn from(variant: AWDIE) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `AWDIE` reader - Analog watchdog interrupt enable
83pub type AWDIE_R = crate::BitReader<AWDIE>;
84impl AWDIE_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> AWDIE {
88        match self.bits {
89            false => AWDIE::Disabled,
90            true => AWDIE::Enabled,
91        }
92    }
93    ///Analog watchdog interrupt disabled
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == AWDIE::Disabled
97    }
98    ///Analog watchdog interrupt enabled
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == AWDIE::Enabled
102    }
103}
104///Field `AWDIE` writer - Analog watchdog interrupt enable
105pub type AWDIE_W<'a, REG> = crate::BitWriter<'a, REG, AWDIE>;
106impl<'a, REG> AWDIE_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Analog watchdog interrupt disabled
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(AWDIE::Disabled)
114    }
115    ///Analog watchdog interrupt enabled
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(AWDIE::Enabled)
119    }
120}
121/**Interrupt enable for injected channels
122
123Value on reset: 0*/
124#[cfg_attr(feature = "defmt", derive(defmt::Format))]
125#[derive(Clone, Copy, Debug, PartialEq, Eq)]
126pub enum JEOCIE {
127    ///0: JEOC interrupt disabled
128    Disabled = 0,
129    ///1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
130    Enabled = 1,
131}
132impl From<JEOCIE> for bool {
133    #[inline(always)]
134    fn from(variant: JEOCIE) -> Self {
135        variant as u8 != 0
136    }
137}
138///Field `JEOCIE` reader - Interrupt enable for injected channels
139pub type JEOCIE_R = crate::BitReader<JEOCIE>;
140impl JEOCIE_R {
141    ///Get enumerated values variant
142    #[inline(always)]
143    pub const fn variant(&self) -> JEOCIE {
144        match self.bits {
145            false => JEOCIE::Disabled,
146            true => JEOCIE::Enabled,
147        }
148    }
149    ///JEOC interrupt disabled
150    #[inline(always)]
151    pub fn is_disabled(&self) -> bool {
152        *self == JEOCIE::Disabled
153    }
154    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
155    #[inline(always)]
156    pub fn is_enabled(&self) -> bool {
157        *self == JEOCIE::Enabled
158    }
159}
160///Field `JEOCIE` writer - Interrupt enable for injected channels
161pub type JEOCIE_W<'a, REG> = crate::BitWriter<'a, REG, JEOCIE>;
162impl<'a, REG> JEOCIE_W<'a, REG>
163where
164    REG: crate::Writable + crate::RegisterSpec,
165{
166    ///JEOC interrupt disabled
167    #[inline(always)]
168    pub fn disabled(self) -> &'a mut crate::W<REG> {
169        self.variant(JEOCIE::Disabled)
170    }
171    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
172    #[inline(always)]
173    pub fn enabled(self) -> &'a mut crate::W<REG> {
174        self.variant(JEOCIE::Enabled)
175    }
176}
177/**Scan mode
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum SCAN {
183    ///0: Scan mode disabled
184    Disabled = 0,
185    ///1: Scan mode enabled
186    Enabled = 1,
187}
188impl From<SCAN> for bool {
189    #[inline(always)]
190    fn from(variant: SCAN) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `SCAN` reader - Scan mode
195pub type SCAN_R = crate::BitReader<SCAN>;
196impl SCAN_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> SCAN {
200        match self.bits {
201            false => SCAN::Disabled,
202            true => SCAN::Enabled,
203        }
204    }
205    ///Scan mode disabled
206    #[inline(always)]
207    pub fn is_disabled(&self) -> bool {
208        *self == SCAN::Disabled
209    }
210    ///Scan mode enabled
211    #[inline(always)]
212    pub fn is_enabled(&self) -> bool {
213        *self == SCAN::Enabled
214    }
215}
216///Field `SCAN` writer - Scan mode
217pub type SCAN_W<'a, REG> = crate::BitWriter<'a, REG, SCAN>;
218impl<'a, REG> SCAN_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///Scan mode disabled
223    #[inline(always)]
224    pub fn disabled(self) -> &'a mut crate::W<REG> {
225        self.variant(SCAN::Disabled)
226    }
227    ///Scan mode enabled
228    #[inline(always)]
229    pub fn enabled(self) -> &'a mut crate::W<REG> {
230        self.variant(SCAN::Enabled)
231    }
232}
233/**Enable the watchdog on a single channel in scan mode
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum AWDSGL {
239    ///0: Analog watchdog enabled on all channels
240    All = 0,
241    ///1: Analog watchdog enabled on a single channel
242    Single = 1,
243}
244impl From<AWDSGL> for bool {
245    #[inline(always)]
246    fn from(variant: AWDSGL) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `AWDSGL` reader - Enable the watchdog on a single channel in scan mode
251pub type AWDSGL_R = crate::BitReader<AWDSGL>;
252impl AWDSGL_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> AWDSGL {
256        match self.bits {
257            false => AWDSGL::All,
258            true => AWDSGL::Single,
259        }
260    }
261    ///Analog watchdog enabled on all channels
262    #[inline(always)]
263    pub fn is_all(&self) -> bool {
264        *self == AWDSGL::All
265    }
266    ///Analog watchdog enabled on a single channel
267    #[inline(always)]
268    pub fn is_single(&self) -> bool {
269        *self == AWDSGL::Single
270    }
271}
272///Field `AWDSGL` writer - Enable the watchdog on a single channel in scan mode
273pub type AWDSGL_W<'a, REG> = crate::BitWriter<'a, REG, AWDSGL>;
274impl<'a, REG> AWDSGL_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Analog watchdog enabled on all channels
279    #[inline(always)]
280    pub fn all(self) -> &'a mut crate::W<REG> {
281        self.variant(AWDSGL::All)
282    }
283    ///Analog watchdog enabled on a single channel
284    #[inline(always)]
285    pub fn single(self) -> &'a mut crate::W<REG> {
286        self.variant(AWDSGL::Single)
287    }
288}
289/**Automatic injected group conversion
290
291Value on reset: 0*/
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum JAUTO {
295    ///0: Automatic injected group conversion disabled
296    Disabled = 0,
297    ///1: Automatic injected group conversion enabled
298    Enabled = 1,
299}
300impl From<JAUTO> for bool {
301    #[inline(always)]
302    fn from(variant: JAUTO) -> Self {
303        variant as u8 != 0
304    }
305}
306///Field `JAUTO` reader - Automatic injected group conversion
307pub type JAUTO_R = crate::BitReader<JAUTO>;
308impl JAUTO_R {
309    ///Get enumerated values variant
310    #[inline(always)]
311    pub const fn variant(&self) -> JAUTO {
312        match self.bits {
313            false => JAUTO::Disabled,
314            true => JAUTO::Enabled,
315        }
316    }
317    ///Automatic injected group conversion disabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == JAUTO::Disabled
321    }
322    ///Automatic injected group conversion enabled
323    #[inline(always)]
324    pub fn is_enabled(&self) -> bool {
325        *self == JAUTO::Enabled
326    }
327}
328///Field `JAUTO` writer - Automatic injected group conversion
329pub type JAUTO_W<'a, REG> = crate::BitWriter<'a, REG, JAUTO>;
330impl<'a, REG> JAUTO_W<'a, REG>
331where
332    REG: crate::Writable + crate::RegisterSpec,
333{
334    ///Automatic injected group conversion disabled
335    #[inline(always)]
336    pub fn disabled(self) -> &'a mut crate::W<REG> {
337        self.variant(JAUTO::Disabled)
338    }
339    ///Automatic injected group conversion enabled
340    #[inline(always)]
341    pub fn enabled(self) -> &'a mut crate::W<REG> {
342        self.variant(JAUTO::Enabled)
343    }
344}
345/**Discontinuous mode on regular channels
346
347Value on reset: 0*/
348#[cfg_attr(feature = "defmt", derive(defmt::Format))]
349#[derive(Clone, Copy, Debug, PartialEq, Eq)]
350pub enum DISCEN {
351    ///0: Discontinuous mode on regular channels disabled
352    Disabled = 0,
353    ///1: Discontinuous mode on regular channels enabled
354    Enabled = 1,
355}
356impl From<DISCEN> for bool {
357    #[inline(always)]
358    fn from(variant: DISCEN) -> Self {
359        variant as u8 != 0
360    }
361}
362///Field `DISCEN` reader - Discontinuous mode on regular channels
363pub type DISCEN_R = crate::BitReader<DISCEN>;
364impl DISCEN_R {
365    ///Get enumerated values variant
366    #[inline(always)]
367    pub const fn variant(&self) -> DISCEN {
368        match self.bits {
369            false => DISCEN::Disabled,
370            true => DISCEN::Enabled,
371        }
372    }
373    ///Discontinuous mode on regular channels disabled
374    #[inline(always)]
375    pub fn is_disabled(&self) -> bool {
376        *self == DISCEN::Disabled
377    }
378    ///Discontinuous mode on regular channels enabled
379    #[inline(always)]
380    pub fn is_enabled(&self) -> bool {
381        *self == DISCEN::Enabled
382    }
383}
384///Field `DISCEN` writer - Discontinuous mode on regular channels
385pub type DISCEN_W<'a, REG> = crate::BitWriter<'a, REG, DISCEN>;
386impl<'a, REG> DISCEN_W<'a, REG>
387where
388    REG: crate::Writable + crate::RegisterSpec,
389{
390    ///Discontinuous mode on regular channels disabled
391    #[inline(always)]
392    pub fn disabled(self) -> &'a mut crate::W<REG> {
393        self.variant(DISCEN::Disabled)
394    }
395    ///Discontinuous mode on regular channels enabled
396    #[inline(always)]
397    pub fn enabled(self) -> &'a mut crate::W<REG> {
398        self.variant(DISCEN::Enabled)
399    }
400}
401/**Discontinuous mode on injected channels
402
403Value on reset: 0*/
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum JDISCEN {
407    ///0: Discontinuous mode on injected channels disabled
408    Disabled = 0,
409    ///1: Discontinuous mode on injected channels enabled
410    Enabled = 1,
411}
412impl From<JDISCEN> for bool {
413    #[inline(always)]
414    fn from(variant: JDISCEN) -> Self {
415        variant as u8 != 0
416    }
417}
418///Field `JDISCEN` reader - Discontinuous mode on injected channels
419pub type JDISCEN_R = crate::BitReader<JDISCEN>;
420impl JDISCEN_R {
421    ///Get enumerated values variant
422    #[inline(always)]
423    pub const fn variant(&self) -> JDISCEN {
424        match self.bits {
425            false => JDISCEN::Disabled,
426            true => JDISCEN::Enabled,
427        }
428    }
429    ///Discontinuous mode on injected channels disabled
430    #[inline(always)]
431    pub fn is_disabled(&self) -> bool {
432        *self == JDISCEN::Disabled
433    }
434    ///Discontinuous mode on injected channels enabled
435    #[inline(always)]
436    pub fn is_enabled(&self) -> bool {
437        *self == JDISCEN::Enabled
438    }
439}
440///Field `JDISCEN` writer - Discontinuous mode on injected channels
441pub type JDISCEN_W<'a, REG> = crate::BitWriter<'a, REG, JDISCEN>;
442impl<'a, REG> JDISCEN_W<'a, REG>
443where
444    REG: crate::Writable + crate::RegisterSpec,
445{
446    ///Discontinuous mode on injected channels disabled
447    #[inline(always)]
448    pub fn disabled(self) -> &'a mut crate::W<REG> {
449        self.variant(JDISCEN::Disabled)
450    }
451    ///Discontinuous mode on injected channels enabled
452    #[inline(always)]
453    pub fn enabled(self) -> &'a mut crate::W<REG> {
454        self.variant(JDISCEN::Enabled)
455    }
456}
457///Field `DISCNUM` reader - Discontinuous mode channel count
458pub type DISCNUM_R = crate::FieldReader;
459///Field `DISCNUM` writer - Discontinuous mode channel count
460pub type DISCNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
461/**Analog watchdog enable on injected channels
462
463Value on reset: 0*/
464#[cfg_attr(feature = "defmt", derive(defmt::Format))]
465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
466pub enum JAWDEN {
467    ///0: Analog watchdog disabled on injected channels
468    Disabled = 0,
469    ///1: Analog watchdog enabled on injected channels
470    Enabled = 1,
471}
472impl From<JAWDEN> for bool {
473    #[inline(always)]
474    fn from(variant: JAWDEN) -> Self {
475        variant as u8 != 0
476    }
477}
478///Field `JAWDEN` reader - Analog watchdog enable on injected channels
479pub type JAWDEN_R = crate::BitReader<JAWDEN>;
480impl JAWDEN_R {
481    ///Get enumerated values variant
482    #[inline(always)]
483    pub const fn variant(&self) -> JAWDEN {
484        match self.bits {
485            false => JAWDEN::Disabled,
486            true => JAWDEN::Enabled,
487        }
488    }
489    ///Analog watchdog disabled on injected channels
490    #[inline(always)]
491    pub fn is_disabled(&self) -> bool {
492        *self == JAWDEN::Disabled
493    }
494    ///Analog watchdog enabled on injected channels
495    #[inline(always)]
496    pub fn is_enabled(&self) -> bool {
497        *self == JAWDEN::Enabled
498    }
499}
500///Field `JAWDEN` writer - Analog watchdog enable on injected channels
501pub type JAWDEN_W<'a, REG> = crate::BitWriter<'a, REG, JAWDEN>;
502impl<'a, REG> JAWDEN_W<'a, REG>
503where
504    REG: crate::Writable + crate::RegisterSpec,
505{
506    ///Analog watchdog disabled on injected channels
507    #[inline(always)]
508    pub fn disabled(self) -> &'a mut crate::W<REG> {
509        self.variant(JAWDEN::Disabled)
510    }
511    ///Analog watchdog enabled on injected channels
512    #[inline(always)]
513    pub fn enabled(self) -> &'a mut crate::W<REG> {
514        self.variant(JAWDEN::Enabled)
515    }
516}
517/**Analog watchdog enable on regular channels
518
519Value on reset: 0*/
520#[cfg_attr(feature = "defmt", derive(defmt::Format))]
521#[derive(Clone, Copy, Debug, PartialEq, Eq)]
522pub enum AWDEN {
523    ///0: Analog watchdog disabled on regular channels
524    Disabled = 0,
525    ///1: Analog watchdog enabled on regular channels
526    Enabled = 1,
527}
528impl From<AWDEN> for bool {
529    #[inline(always)]
530    fn from(variant: AWDEN) -> Self {
531        variant as u8 != 0
532    }
533}
534///Field `AWDEN` reader - Analog watchdog enable on regular channels
535pub type AWDEN_R = crate::BitReader<AWDEN>;
536impl AWDEN_R {
537    ///Get enumerated values variant
538    #[inline(always)]
539    pub const fn variant(&self) -> AWDEN {
540        match self.bits {
541            false => AWDEN::Disabled,
542            true => AWDEN::Enabled,
543        }
544    }
545    ///Analog watchdog disabled on regular channels
546    #[inline(always)]
547    pub fn is_disabled(&self) -> bool {
548        *self == AWDEN::Disabled
549    }
550    ///Analog watchdog enabled on regular channels
551    #[inline(always)]
552    pub fn is_enabled(&self) -> bool {
553        *self == AWDEN::Enabled
554    }
555}
556///Field `AWDEN` writer - Analog watchdog enable on regular channels
557pub type AWDEN_W<'a, REG> = crate::BitWriter<'a, REG, AWDEN>;
558impl<'a, REG> AWDEN_W<'a, REG>
559where
560    REG: crate::Writable + crate::RegisterSpec,
561{
562    ///Analog watchdog disabled on regular channels
563    #[inline(always)]
564    pub fn disabled(self) -> &'a mut crate::W<REG> {
565        self.variant(AWDEN::Disabled)
566    }
567    ///Analog watchdog enabled on regular channels
568    #[inline(always)]
569    pub fn enabled(self) -> &'a mut crate::W<REG> {
570        self.variant(AWDEN::Enabled)
571    }
572}
573impl R {
574    ///Bits 0:4 - Analog watchdog channel select bits
575    #[inline(always)]
576    pub fn awdch(&self) -> AWDCH_R {
577        AWDCH_R::new((self.bits & 0x1f) as u8)
578    }
579    ///Bit 5 - Interrupt enable for EOC
580    #[inline(always)]
581    pub fn eocie(&self) -> EOCIE_R {
582        EOCIE_R::new(((self.bits >> 5) & 1) != 0)
583    }
584    ///Bit 6 - Analog watchdog interrupt enable
585    #[inline(always)]
586    pub fn awdie(&self) -> AWDIE_R {
587        AWDIE_R::new(((self.bits >> 6) & 1) != 0)
588    }
589    ///Bit 7 - Interrupt enable for injected channels
590    #[inline(always)]
591    pub fn jeocie(&self) -> JEOCIE_R {
592        JEOCIE_R::new(((self.bits >> 7) & 1) != 0)
593    }
594    ///Bit 8 - Scan mode
595    #[inline(always)]
596    pub fn scan(&self) -> SCAN_R {
597        SCAN_R::new(((self.bits >> 8) & 1) != 0)
598    }
599    ///Bit 9 - Enable the watchdog on a single channel in scan mode
600    #[inline(always)]
601    pub fn awdsgl(&self) -> AWDSGL_R {
602        AWDSGL_R::new(((self.bits >> 9) & 1) != 0)
603    }
604    ///Bit 10 - Automatic injected group conversion
605    #[inline(always)]
606    pub fn jauto(&self) -> JAUTO_R {
607        JAUTO_R::new(((self.bits >> 10) & 1) != 0)
608    }
609    ///Bit 11 - Discontinuous mode on regular channels
610    #[inline(always)]
611    pub fn discen(&self) -> DISCEN_R {
612        DISCEN_R::new(((self.bits >> 11) & 1) != 0)
613    }
614    ///Bit 12 - Discontinuous mode on injected channels
615    #[inline(always)]
616    pub fn jdiscen(&self) -> JDISCEN_R {
617        JDISCEN_R::new(((self.bits >> 12) & 1) != 0)
618    }
619    ///Bits 13:15 - Discontinuous mode channel count
620    #[inline(always)]
621    pub fn discnum(&self) -> DISCNUM_R {
622        DISCNUM_R::new(((self.bits >> 13) & 7) as u8)
623    }
624    ///Bit 22 - Analog watchdog enable on injected channels
625    #[inline(always)]
626    pub fn jawden(&self) -> JAWDEN_R {
627        JAWDEN_R::new(((self.bits >> 22) & 1) != 0)
628    }
629    ///Bit 23 - Analog watchdog enable on regular channels
630    #[inline(always)]
631    pub fn awden(&self) -> AWDEN_R {
632        AWDEN_R::new(((self.bits >> 23) & 1) != 0)
633    }
634}
635impl core::fmt::Debug for R {
636    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
637        f.debug_struct("CR1")
638            .field("awden", &self.awden())
639            .field("jawden", &self.jawden())
640            .field("discnum", &self.discnum())
641            .field("jdiscen", &self.jdiscen())
642            .field("discen", &self.discen())
643            .field("jauto", &self.jauto())
644            .field("awdsgl", &self.awdsgl())
645            .field("scan", &self.scan())
646            .field("jeocie", &self.jeocie())
647            .field("awdie", &self.awdie())
648            .field("eocie", &self.eocie())
649            .field("awdch", &self.awdch())
650            .finish()
651    }
652}
653impl W {
654    ///Bits 0:4 - Analog watchdog channel select bits
655    #[inline(always)]
656    pub fn awdch(&mut self) -> AWDCH_W<CR1rs> {
657        AWDCH_W::new(self, 0)
658    }
659    ///Bit 5 - Interrupt enable for EOC
660    #[inline(always)]
661    pub fn eocie(&mut self) -> EOCIE_W<CR1rs> {
662        EOCIE_W::new(self, 5)
663    }
664    ///Bit 6 - Analog watchdog interrupt enable
665    #[inline(always)]
666    pub fn awdie(&mut self) -> AWDIE_W<CR1rs> {
667        AWDIE_W::new(self, 6)
668    }
669    ///Bit 7 - Interrupt enable for injected channels
670    #[inline(always)]
671    pub fn jeocie(&mut self) -> JEOCIE_W<CR1rs> {
672        JEOCIE_W::new(self, 7)
673    }
674    ///Bit 8 - Scan mode
675    #[inline(always)]
676    pub fn scan(&mut self) -> SCAN_W<CR1rs> {
677        SCAN_W::new(self, 8)
678    }
679    ///Bit 9 - Enable the watchdog on a single channel in scan mode
680    #[inline(always)]
681    pub fn awdsgl(&mut self) -> AWDSGL_W<CR1rs> {
682        AWDSGL_W::new(self, 9)
683    }
684    ///Bit 10 - Automatic injected group conversion
685    #[inline(always)]
686    pub fn jauto(&mut self) -> JAUTO_W<CR1rs> {
687        JAUTO_W::new(self, 10)
688    }
689    ///Bit 11 - Discontinuous mode on regular channels
690    #[inline(always)]
691    pub fn discen(&mut self) -> DISCEN_W<CR1rs> {
692        DISCEN_W::new(self, 11)
693    }
694    ///Bit 12 - Discontinuous mode on injected channels
695    #[inline(always)]
696    pub fn jdiscen(&mut self) -> JDISCEN_W<CR1rs> {
697        JDISCEN_W::new(self, 12)
698    }
699    ///Bits 13:15 - Discontinuous mode channel count
700    #[inline(always)]
701    pub fn discnum(&mut self) -> DISCNUM_W<CR1rs> {
702        DISCNUM_W::new(self, 13)
703    }
704    ///Bit 22 - Analog watchdog enable on injected channels
705    #[inline(always)]
706    pub fn jawden(&mut self) -> JAWDEN_W<CR1rs> {
707        JAWDEN_W::new(self, 22)
708    }
709    ///Bit 23 - Analog watchdog enable on regular channels
710    #[inline(always)]
711    pub fn awden(&mut self) -> AWDEN_W<CR1rs> {
712        AWDEN_W::new(self, 23)
713    }
714}
715/**control register 1
716
717You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
718
719See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#ADC1:CR1)*/
720pub struct CR1rs;
721impl crate::RegisterSpec for CR1rs {
722    type Ux = u32;
723}
724///`read()` method returns [`cr1::R`](R) reader structure
725impl crate::Readable for CR1rs {}
726///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
727impl crate::Writable for CR1rs {
728    type Safety = crate::Unsafe;
729}
730///`reset()` method sets CR1 to value 0
731impl crate::Resettable for CR1rs {}
stm32f1_staging/stm32f100/adc1/cr1.rs

stm32f1_staging/stm32f100/adc1/
cr1.rs
