Module stm32f0xx::rcc
[−]
[src]
Reset and clock control
Modules
| ahbenr |
AHB Peripheral Clock enable register(RCC_AHBENR) |
| ahbrstr |
AHB peripheral reset register |
| apb1enr |
APB1 peripheral clock enable register(RCC_APB1ENR) |
| apb1rstr |
APB1 peripheral reset register(RCC_APB1RSTR) |
| apb2enr |
APB2 peripheral clock enable register(RCC_APB2ENR) |
| apb2rstr |
APB2 peripheral reset register(RCC_APB2RSTR) |
| bdcr |
Backup domain control register(RCC_BDCR) |
| cfgr |
Clock configuration register(RCC_CFGR) |
| cfgr2 |
Clock configuration register 2 |
| cfgr3 |
Clock configuration register 3 |
| cir |
Clock interrupt register(RCC_CIR) |
| cr |
Clock control register |
| cr2 |
Clock control register 2 |
| csr |
Control/status register(RCC_CSR) |
Structs
| Ahbenr |
AHB Peripheral Clock enable register(RCC_AHBENR) |
| Ahbrstr |
AHB peripheral reset register |
| Apb1enr |
APB1 peripheral clock enable register(RCC_APB1ENR) |
| Apb1rstr |
APB1 peripheral reset register(RCC_APB1RSTR) |
| Apb2enr |
APB2 peripheral clock enable register(RCC_APB2ENR) |
| Apb2rstr |
APB2 peripheral reset register(RCC_APB2RSTR) |
| Bdcr |
Backup domain control register(RCC_BDCR) |
| Cfgr |
Clock configuration register(RCC_CFGR) |
| Cfgr2 |
Clock configuration register 2 |
| Cfgr3 |
Clock configuration register 3 |
| Cir |
Clock interrupt register(RCC_CIR) |
| Cr |
Clock control register |
| Cr2 |
Clock control register 2 |
| Csr |
Control/status register(RCC_CSR) |
| RegisterBlock |
Register block |