Struct stm32f0xx_hal::pac::tim15::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock {
Show 16 fields pub cr1: Reg<CR1_SPEC>, pub cr2: Reg<CR2_SPEC>, pub smcr: Reg<SMCR_SPEC>, pub dier: Reg<DIER_SPEC>, pub sr: Reg<SR_SPEC>, pub egr: Reg<EGR_SPEC>, pub ccer: Reg<CCER_SPEC>, pub cnt: Reg<CNT_SPEC>, pub psc: Reg<PSC_SPEC>, pub arr: Reg<ARR_SPEC>, pub rcr: Reg<RCR_SPEC>, pub ccr1: Reg<CCR_SPEC>, pub ccr2: Reg<CCR_SPEC>, pub bdtr: Reg<BDTR_SPEC>, pub dcr: Reg<DCR_SPEC>, pub dmar: Reg<DMAR_SPEC>, // some fields omitted
}
Expand description

Register block

Fields

cr1: Reg<CR1_SPEC>

0x00 - control register 1

cr2: Reg<CR2_SPEC>

0x04 - control register 2

smcr: Reg<SMCR_SPEC>

0x08 - slave mode control register

dier: Reg<DIER_SPEC>

0x0c - DMA/Interrupt enable register

sr: Reg<SR_SPEC>

0x10 - status register

egr: Reg<EGR_SPEC>

0x14 - event generation register

ccer: Reg<CCER_SPEC>

0x20 - capture/compare enable register

cnt: Reg<CNT_SPEC>

0x24 - counter

psc: Reg<PSC_SPEC>

0x28 - prescaler

arr: Reg<ARR_SPEC>

0x2c - auto-reload register

rcr: Reg<RCR_SPEC>

0x30 - repetition counter register

ccr1: Reg<CCR_SPEC>

0x34 - capture/compare register

ccr2: Reg<CCR_SPEC>

0x38 - capture/compare register

bdtr: Reg<BDTR_SPEC>

0x44 - break and dead-time register

dcr: Reg<DCR_SPEC>

0x48 - DMA control register

dmar: Reg<DMAR_SPEC>

0x4c - DMA address for full transfer

Implementations

0x18 - capture/compare mode register 1 (input mode)

0x18 - capture/compare mode register (output mode)

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