Struct stm32f0xx_hal::pac::SCB [−][src]
pub struct SCB { /* fields omitted */ }
Expand description
System Control Block
Implementations
Returns the active exception number
Set the SLEEPDEEP bit in the SCR register
Clear the SLEEPDEEP bit in the SCR register
Set the SLEEPONEXIT bit in the SCR register
Clear the SLEEPONEXIT bit in the SCR register
Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt
Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending
Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt
Set the PENDSTSET bit in the ICSR register which will pend a SysTick interrupt
Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
Returns the hardware priority of system_handler
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
Sets the hardware priority of system_handler
to prio
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On ARMv7-M, the operation is performed in a single, atomic write operation.
Unsafety
Changing priority levels can break priority-based critical sections (see
register::basepri
) and compromise memory safety.
Pointer to the register block
Returns a pointer to the register block (to be deprecated in 0.7)