Enum stm32f0xx_hal::pac::wwdg::cfr::WDGTB_A [−][src]
#[repr(u8)]
pub enum WDGTB_A {
DIV1,
DIV2,
DIV4,
DIV8,
}
Expand description
Timer base
Value on reset: 0
Variants
0: Counter clock (PCLK1 div 4096) div 1
1: Counter clock (PCLK1 div 4096) div 2
2: Counter clock (PCLK1 div 4096) div 4
3: Counter clock (PCLK1 div 4096) div 8