Enum stm32f0xx_hal::pac::tim16::cr1::URS_A [−][src]
pub enum URS_A {
ANYEVENT,
COUNTERONLY,
}
Expand description
Update request source
Value on reset: 0
Variants
0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: Only counter overflow/underflow generates an update interrupt or DMA request