Struct stm32f0xx_hal::pac::dac::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 14 fields
pub cr: Reg<CR_SPEC>,
pub swtrigr: Reg<SWTRIGR_SPEC>,
pub dhr12r1: Reg<DHR12R1_SPEC>,
pub dhr12l1: Reg<DHR12L1_SPEC>,
pub dhr8r1: Reg<DHR8R1_SPEC>,
pub dhr12r2: Reg<DHR12R2_SPEC>,
pub dhr12l2: Reg<DHR12L2_SPEC>,
pub dhr8r2: Reg<DHR8R2_SPEC>,
pub dhr12rd: Reg<DHR12RD_SPEC>,
pub dhr12ld: Reg<DHR12LD_SPEC>,
pub dhr8rd: Reg<DHR8RD_SPEC>,
pub dor1: Reg<DOR1_SPEC>,
pub dor2: Reg<DOR2_SPEC>,
pub sr: Reg<SR_SPEC>,
}
Expand description
Register block
Fields
cr: Reg<CR_SPEC>
0x00 - control register
swtrigr: Reg<SWTRIGR_SPEC>
0x04 - software trigger register
dhr12r1: Reg<DHR12R1_SPEC>
0x08 - channel1 12-bit right-aligned data holding register
dhr12l1: Reg<DHR12L1_SPEC>
0x0c - channel1 12-bit left aligned data holding register
dhr8r1: Reg<DHR8R1_SPEC>
0x10 - channel1 8-bit right aligned data holding register
dhr12r2: Reg<DHR12R2_SPEC>
0x14 - DAC channel2 12-bit right-aligned data holding register
dhr12l2: Reg<DHR12L2_SPEC>
0x18 - DAC channel2 12-bit left-aligned data holding register
dhr8r2: Reg<DHR8R2_SPEC>
0x1c - DAC channel2 8-bit right-aligned data holding register
dhr12rd: Reg<DHR12RD_SPEC>
0x20 - DHR12RD
dhr12ld: Reg<DHR12LD_SPEC>
0x24 - Dual DAC 12-bit left-aligned data holding register
dhr8rd: Reg<DHR8RD_SPEC>
0x28 - Dual DAC 8-bit right-aligned data holding register
dor1: Reg<DOR1_SPEC>
0x2c - channel1 data output register
dor2: Reg<DOR2_SPEC>
0x30 - DAC channel2 data output register
sr: Reg<SR_SPEC>
0x34 - status register