[][src]Enum stm32f0xx_hal::pac::usart1::cr2::TXINV_A

pub enum TXINV_A {
    STANDARD,
    INVERTED,
}

TX pin active level inversion

Value on reset: 0

Variants

STANDARD

0: TX pin signal works using the standard logic levels

INVERTED

1: TX pin signal values are inverted

Trait Implementations

impl Clone for TXINV_A[src]

impl Copy for TXINV_A[src]

impl Debug for TXINV_A[src]

impl PartialEq<TXINV_A> for TXINV_A[src]

Auto Trait Implementations

impl Send for TXINV_A

impl Sync for TXINV_A

impl Unpin for TXINV_A

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.