[−][src]Struct stm32f0xx_hal::pac::tim16::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cr1: Reg<u32, _CR1>,
    pub cr2: Reg<u32, _CR2>,
    pub dier: Reg<u32, _DIER>,
    pub sr: Reg<u32, _SR>,
    pub egr: Reg<u32, _EGR>,
    pub ccer: Reg<u32, _CCER>,
    pub cnt: Reg<u32, _CNT>,
    pub psc: Reg<u32, _PSC>,
    pub arr: Reg<u32, _ARR>,
    pub rcr: Reg<u32, _RCR>,
    pub ccr1: Reg<u32, _CCR1>,
    pub bdtr: Reg<u32, _BDTR>,
    pub dcr: Reg<u32, _DCR>,
    pub dmar: Reg<u32, _DMAR>,
    // some fields omitted
}

Register block

Fields

cr1: Reg<u32, _CR1>

0x00 - control register 1

cr2: Reg<u32, _CR2>

0x04 - control register 2

dier: Reg<u32, _DIER>

0x0c - DMA/Interrupt enable register

sr: Reg<u32, _SR>

0x10 - status register

egr: Reg<u32, _EGR>

0x14 - event generation register

ccer: Reg<u32, _CCER>

0x20 - capture/compare enable register

cnt: Reg<u32, _CNT>

0x24 - counter

psc: Reg<u32, _PSC>

0x28 - prescaler

arr: Reg<u32, _ARR>

0x2c - auto-reload register

rcr: Reg<u32, _RCR>

0x30 - repetition counter register

ccr1: Reg<u32, _CCR1>

0x34 - capture/compare register 1

bdtr: Reg<u32, _BDTR>

0x44 - break and dead-time register

dcr: Reg<u32, _DCR>

0x48 - DMA control register

dmar: Reg<u32, _DMAR>

0x4c - DMA address for full transfer

Implementations

impl RegisterBlock[src]

pub fn ccmr1_input(&self) -> &Reg<u32, _CCMR1_INPUT>[src]

0x18 - capture/compare mode register 1 (input mode)

pub fn ccmr1_input_mut(&self) -> &mut Reg<u32, _CCMR1_INPUT>[src]

0x18 - capture/compare mode register 1 (input mode)

pub fn ccmr1_output(&self) -> &Reg<u32, _CCMR1_OUTPUT>[src]

0x18 - capture/compare mode register (output mode)

pub fn ccmr1_output_mut(&self) -> &mut Reg<u32, _CCMR1_OUTPUT>[src]

0x18 - capture/compare mode register (output mode)

Auto Trait Implementations

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    T: 'static + ?Sized, [src]

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    T: ?Sized, [src]

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    T: ?Sized, [src]

impl<T> From<T> for T[src]

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    U: From<T>, [src]

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    U: Into<T>, [src]

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    U: TryFrom<T>, [src]

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