Enum stm32f0xx_hal::stm32::tim2::cr2::MMSR

pub enum MMSR {
    RESET,
    ENABLE,
    UPDATE,
    COMPAREPULSE,
    COMPAREOC1,
    COMPAREOC2,
    COMPAREOC3,
    COMPAREOC4,
}

Possible values of the field MMS

Variants

RESET

The UG bit from the TIMx_EGR register is used as trigger output

ENABLE

The counter enable signal, CNT_EN, is used as trigger output

UPDATE

The update event is selected as trigger output

COMPAREPULSE

The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred

COMPAREOC1

OC1REF signal is used as trigger output

COMPAREOC2

OC2REF signal is used as trigger output

COMPAREOC3

OC3REF signal is used as trigger output

COMPAREOC4

OC4REF signal is used as trigger output

Methods

impl MMSR

pub fn bits(&self) -> u8

Value of the field as raw bits

pub fn is_reset(&self) -> bool

Checks if the value of the field is RESET

pub fn is_enable(&self) -> bool

Checks if the value of the field is ENABLE

pub fn is_update(&self) -> bool

Checks if the value of the field is UPDATE

pub fn is_compare_pulse(&self) -> bool

Checks if the value of the field is COMPAREPULSE

pub fn is_compare_oc1(&self) -> bool

Checks if the value of the field is COMPAREOC1

pub fn is_compare_oc2(&self) -> bool

Checks if the value of the field is COMPAREOC2

pub fn is_compare_oc3(&self) -> bool

Checks if the value of the field is COMPAREOC3

pub fn is_compare_oc4(&self) -> bool

Checks if the value of the field is COMPAREOC4

Trait Implementations

impl PartialEq<MMSR> for MMSR

fn eq(&self, other: &MMSR) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Clone for MMSR

fn clone(&self) -> MMSR

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for MMSR

impl Debug for MMSR

fn fmt(&self, f: &mut Formatter) -> Result<(), Error>

Formats the value using the given formatter.