stm32f0/stm32f0x8/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5/**LATENCY
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum LATENCY {
12    ///0: 0 wait states
13    Ws0 = 0,
14    ///1: 1 wait state
15    Ws1 = 1,
16}
17impl From<LATENCY> for u8 {
18    #[inline(always)]
19    fn from(variant: LATENCY) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for LATENCY {
24    type Ux = u8;
25}
26impl crate::IsEnum for LATENCY {}
27///Field `LATENCY` reader - LATENCY
28pub type LATENCY_R = crate::FieldReader<LATENCY>;
29impl LATENCY_R {
30    ///Get enumerated values variant
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<LATENCY> {
33        match self.bits {
34            0 => Some(LATENCY::Ws0),
35            1 => Some(LATENCY::Ws1),
36            _ => None,
37        }
38    }
39    ///0 wait states
40    #[inline(always)]
41    pub fn is_ws0(&self) -> bool {
42        *self == LATENCY::Ws0
43    }
44    ///1 wait state
45    #[inline(always)]
46    pub fn is_ws1(&self) -> bool {
47        *self == LATENCY::Ws1
48    }
49}
50///Field `LATENCY` writer - LATENCY
51pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 3, LATENCY>;
52impl<'a, REG> LATENCY_W<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55    REG::Ux: From<u8>,
56{
57    ///0 wait states
58    #[inline(always)]
59    pub fn ws0(self) -> &'a mut crate::W<REG> {
60        self.variant(LATENCY::Ws0)
61    }
62    ///1 wait state
63    #[inline(always)]
64    pub fn ws1(self) -> &'a mut crate::W<REG> {
65        self.variant(LATENCY::Ws1)
66    }
67}
68/**PRFTBE
69
70Value on reset: 1*/
71#[cfg_attr(feature = "defmt", derive(defmt::Format))]
72#[derive(Clone, Copy, Debug, PartialEq, Eq)]
73pub enum PRFTBE {
74    ///0: Prefetch is disabled
75    Disabled = 0,
76    ///1: Prefetch is enabled
77    Enabled = 1,
78}
79impl From<PRFTBE> for bool {
80    #[inline(always)]
81    fn from(variant: PRFTBE) -> Self {
82        variant as u8 != 0
83    }
84}
85///Field `PRFTBE` reader - PRFTBE
86pub type PRFTBE_R = crate::BitReader<PRFTBE>;
87impl PRFTBE_R {
88    ///Get enumerated values variant
89    #[inline(always)]
90    pub const fn variant(&self) -> PRFTBE {
91        match self.bits {
92            false => PRFTBE::Disabled,
93            true => PRFTBE::Enabled,
94        }
95    }
96    ///Prefetch is disabled
97    #[inline(always)]
98    pub fn is_disabled(&self) -> bool {
99        *self == PRFTBE::Disabled
100    }
101    ///Prefetch is enabled
102    #[inline(always)]
103    pub fn is_enabled(&self) -> bool {
104        *self == PRFTBE::Enabled
105    }
106}
107///Field `PRFTBE` writer - PRFTBE
108pub type PRFTBE_W<'a, REG> = crate::BitWriter<'a, REG, PRFTBE>;
109impl<'a, REG> PRFTBE_W<'a, REG>
110where
111    REG: crate::Writable + crate::RegisterSpec,
112{
113    ///Prefetch is disabled
114    #[inline(always)]
115    pub fn disabled(self) -> &'a mut crate::W<REG> {
116        self.variant(PRFTBE::Disabled)
117    }
118    ///Prefetch is enabled
119    #[inline(always)]
120    pub fn enabled(self) -> &'a mut crate::W<REG> {
121        self.variant(PRFTBE::Enabled)
122    }
123}
124/**PRFTBS
125
126Value on reset: 1*/
127#[cfg_attr(feature = "defmt", derive(defmt::Format))]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129pub enum PRFTBSR {
130    ///0: Prefetch buffer is disabled
131    Disabled = 0,
132    ///1: Prefetch buffer is enabled
133    Enabled = 1,
134}
135impl From<PRFTBSR> for bool {
136    #[inline(always)]
137    fn from(variant: PRFTBSR) -> Self {
138        variant as u8 != 0
139    }
140}
141///Field `PRFTBS` reader - PRFTBS
142pub type PRFTBS_R = crate::BitReader<PRFTBSR>;
143impl PRFTBS_R {
144    ///Get enumerated values variant
145    #[inline(always)]
146    pub const fn variant(&self) -> PRFTBSR {
147        match self.bits {
148            false => PRFTBSR::Disabled,
149            true => PRFTBSR::Enabled,
150        }
151    }
152    ///Prefetch buffer is disabled
153    #[inline(always)]
154    pub fn is_disabled(&self) -> bool {
155        *self == PRFTBSR::Disabled
156    }
157    ///Prefetch buffer is enabled
158    #[inline(always)]
159    pub fn is_enabled(&self) -> bool {
160        *self == PRFTBSR::Enabled
161    }
162}
163impl R {
164    ///Bits 0:2 - LATENCY
165    #[inline(always)]
166    pub fn latency(&self) -> LATENCY_R {
167        LATENCY_R::new((self.bits & 7) as u8)
168    }
169    ///Bit 4 - PRFTBE
170    #[inline(always)]
171    pub fn prftbe(&self) -> PRFTBE_R {
172        PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
173    }
174    ///Bit 5 - PRFTBS
175    #[inline(always)]
176    pub fn prftbs(&self) -> PRFTBS_R {
177        PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
178    }
179}
180impl core::fmt::Debug for R {
181    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
182        f.debug_struct("ACR")
183            .field("latency", &self.latency())
184            .field("prftbe", &self.prftbe())
185            .field("prftbs", &self.prftbs())
186            .finish()
187    }
188}
189impl W {
190    ///Bits 0:2 - LATENCY
191    #[inline(always)]
192    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
193        LATENCY_W::new(self, 0)
194    }
195    ///Bit 4 - PRFTBE
196    #[inline(always)]
197    pub fn prftbe(&mut self) -> PRFTBE_W<ACRrs> {
198        PRFTBE_W::new(self, 4)
199    }
200}
201/**Flash access control register
202
203You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
204
205See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x8.html#Flash:ACR)*/
206pub struct ACRrs;
207impl crate::RegisterSpec for ACRrs {
208    type Ux = u32;
209}
210///`read()` method returns [`acr::R`](R) reader structure
211impl crate::Readable for ACRrs {}
212///`write(|w| ..)` method takes [`acr::W`](W) writer structure
213impl crate::Writable for ACRrs {
214    type Safety = crate::Unsafe;
215}
216///`reset()` method sets ACR to value 0x30
217impl crate::Resettable for ACRrs {
218    const RESET_VALUE: u32 = 0x30;
219}
stm32f0/stm32f0x8/flash/acr.rs

stm32f0/stm32f0x8/flash/
acr.rs
