stm32f0/stm32f0x2/tim1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Capture/compare preloaded control
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CCPC {
11    ///0: CCxE, CCxNE and OCxM bits are not preloaded
12    NotPreloaded = 0,
13    ///1: CCxE, CCxNE and OCxM bits are preloaded
14    Preloaded = 1,
15}
16impl From<CCPC> for bool {
17    #[inline(always)]
18    fn from(variant: CCPC) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCPC` reader - Capture/compare preloaded control
23pub type CCPC_R = crate::BitReader<CCPC>;
24impl CCPC_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CCPC {
28        match self.bits {
29            false => CCPC::NotPreloaded,
30            true => CCPC::Preloaded,
31        }
32    }
33    ///CCxE, CCxNE and OCxM bits are not preloaded
34    #[inline(always)]
35    pub fn is_not_preloaded(&self) -> bool {
36        *self == CCPC::NotPreloaded
37    }
38    ///CCxE, CCxNE and OCxM bits are preloaded
39    #[inline(always)]
40    pub fn is_preloaded(&self) -> bool {
41        *self == CCPC::Preloaded
42    }
43}
44///Field `CCPC` writer - Capture/compare preloaded control
45pub type CCPC_W<'a, REG> = crate::BitWriter<'a, REG, CCPC>;
46impl<'a, REG> CCPC_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///CCxE, CCxNE and OCxM bits are not preloaded
51    #[inline(always)]
52    pub fn not_preloaded(self) -> &'a mut crate::W<REG> {
53        self.variant(CCPC::NotPreloaded)
54    }
55    ///CCxE, CCxNE and OCxM bits are preloaded
56    #[inline(always)]
57    pub fn preloaded(self) -> &'a mut crate::W<REG> {
58        self.variant(CCPC::Preloaded)
59    }
60}
61/**Capture/compare control update selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CCUS {
67    ///0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
68    Sw = 0,
69    ///1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
70    SwOrEdge = 1,
71}
72impl From<CCUS> for bool {
73    #[inline(always)]
74    fn from(variant: CCUS) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCUS` reader - Capture/compare control update selection
79pub type CCUS_R = crate::BitReader<CCUS>;
80impl CCUS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CCUS {
84        match self.bits {
85            false => CCUS::Sw,
86            true => CCUS::SwOrEdge,
87        }
88    }
89    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
90    #[inline(always)]
91    pub fn is_sw(&self) -> bool {
92        *self == CCUS::Sw
93    }
94    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
95    #[inline(always)]
96    pub fn is_sw_or_edge(&self) -> bool {
97        *self == CCUS::SwOrEdge
98    }
99}
100///Field `CCUS` writer - Capture/compare control update selection
101pub type CCUS_W<'a, REG> = crate::BitWriter<'a, REG, CCUS>;
102impl<'a, REG> CCUS_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
107    #[inline(always)]
108    pub fn sw(self) -> &'a mut crate::W<REG> {
109        self.variant(CCUS::Sw)
110    }
111    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
112    #[inline(always)]
113    pub fn sw_or_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CCUS::SwOrEdge)
115    }
116}
117/**Capture/compare DMA selection
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CCDS {
123    ///0: CCx DMA request sent when CCx event occurs
124    OnCompare = 0,
125    ///1: CCx DMA request sent when update event occurs
126    OnUpdate = 1,
127}
128impl From<CCDS> for bool {
129    #[inline(always)]
130    fn from(variant: CCDS) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCDS` reader - Capture/compare DMA selection
135pub type CCDS_R = crate::BitReader<CCDS>;
136impl CCDS_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CCDS {
140        match self.bits {
141            false => CCDS::OnCompare,
142            true => CCDS::OnUpdate,
143        }
144    }
145    ///CCx DMA request sent when CCx event occurs
146    #[inline(always)]
147    pub fn is_on_compare(&self) -> bool {
148        *self == CCDS::OnCompare
149    }
150    ///CCx DMA request sent when update event occurs
151    #[inline(always)]
152    pub fn is_on_update(&self) -> bool {
153        *self == CCDS::OnUpdate
154    }
155}
156///Field `CCDS` writer - Capture/compare DMA selection
157pub type CCDS_W<'a, REG> = crate::BitWriter<'a, REG, CCDS>;
158impl<'a, REG> CCDS_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///CCx DMA request sent when CCx event occurs
163    #[inline(always)]
164    pub fn on_compare(self) -> &'a mut crate::W<REG> {
165        self.variant(CCDS::OnCompare)
166    }
167    ///CCx DMA request sent when update event occurs
168    #[inline(always)]
169    pub fn on_update(self) -> &'a mut crate::W<REG> {
170        self.variant(CCDS::OnUpdate)
171    }
172}
173/**Master mode selection
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178#[repr(u8)]
179pub enum MMS {
180    ///0: The UG bit from the TIMx_EGR register is used as trigger output
181    Reset = 0,
182    ///1: The counter enable signal, CNT_EN, is used as trigger output
183    Enable = 1,
184    ///2: The update event is selected as trigger output
185    Update = 2,
186    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
187    ComparePulse = 3,
188    ///4: OC1REF signal is used as trigger output
189    CompareOc1 = 4,
190    ///5: OC2REF signal is used as trigger output
191    CompareOc2 = 5,
192    ///6: OC3REF signal is used as trigger output
193    CompareOc3 = 6,
194    ///7: OC4REF signal is used as trigger output
195    CompareOc4 = 7,
196}
197impl From<MMS> for u8 {
198    #[inline(always)]
199    fn from(variant: MMS) -> Self {
200        variant as _
201    }
202}
203impl crate::FieldSpec for MMS {
204    type Ux = u8;
205}
206impl crate::IsEnum for MMS {}
207///Field `MMS` reader - Master mode selection
208pub type MMS_R = crate::FieldReader<MMS>;
209impl MMS_R {
210    ///Get enumerated values variant
211    #[inline(always)]
212    pub const fn variant(&self) -> MMS {
213        match self.bits {
214            0 => MMS::Reset,
215            1 => MMS::Enable,
216            2 => MMS::Update,
217            3 => MMS::ComparePulse,
218            4 => MMS::CompareOc1,
219            5 => MMS::CompareOc2,
220            6 => MMS::CompareOc3,
221            7 => MMS::CompareOc4,
222            _ => unreachable!(),
223        }
224    }
225    ///The UG bit from the TIMx_EGR register is used as trigger output
226    #[inline(always)]
227    pub fn is_reset(&self) -> bool {
228        *self == MMS::Reset
229    }
230    ///The counter enable signal, CNT_EN, is used as trigger output
231    #[inline(always)]
232    pub fn is_enable(&self) -> bool {
233        *self == MMS::Enable
234    }
235    ///The update event is selected as trigger output
236    #[inline(always)]
237    pub fn is_update(&self) -> bool {
238        *self == MMS::Update
239    }
240    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
241    #[inline(always)]
242    pub fn is_compare_pulse(&self) -> bool {
243        *self == MMS::ComparePulse
244    }
245    ///OC1REF signal is used as trigger output
246    #[inline(always)]
247    pub fn is_compare_oc1(&self) -> bool {
248        *self == MMS::CompareOc1
249    }
250    ///OC2REF signal is used as trigger output
251    #[inline(always)]
252    pub fn is_compare_oc2(&self) -> bool {
253        *self == MMS::CompareOc2
254    }
255    ///OC3REF signal is used as trigger output
256    #[inline(always)]
257    pub fn is_compare_oc3(&self) -> bool {
258        *self == MMS::CompareOc3
259    }
260    ///OC4REF signal is used as trigger output
261    #[inline(always)]
262    pub fn is_compare_oc4(&self) -> bool {
263        *self == MMS::CompareOc4
264    }
265}
266///Field `MMS` writer - Master mode selection
267pub type MMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MMS, crate::Safe>;
268impl<'a, REG> MMS_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271    REG::Ux: From<u8>,
272{
273    ///The UG bit from the TIMx_EGR register is used as trigger output
274    #[inline(always)]
275    pub fn reset(self) -> &'a mut crate::W<REG> {
276        self.variant(MMS::Reset)
277    }
278    ///The counter enable signal, CNT_EN, is used as trigger output
279    #[inline(always)]
280    pub fn enable(self) -> &'a mut crate::W<REG> {
281        self.variant(MMS::Enable)
282    }
283    ///The update event is selected as trigger output
284    #[inline(always)]
285    pub fn update(self) -> &'a mut crate::W<REG> {
286        self.variant(MMS::Update)
287    }
288    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
289    #[inline(always)]
290    pub fn compare_pulse(self) -> &'a mut crate::W<REG> {
291        self.variant(MMS::ComparePulse)
292    }
293    ///OC1REF signal is used as trigger output
294    #[inline(always)]
295    pub fn compare_oc1(self) -> &'a mut crate::W<REG> {
296        self.variant(MMS::CompareOc1)
297    }
298    ///OC2REF signal is used as trigger output
299    #[inline(always)]
300    pub fn compare_oc2(self) -> &'a mut crate::W<REG> {
301        self.variant(MMS::CompareOc2)
302    }
303    ///OC3REF signal is used as trigger output
304    #[inline(always)]
305    pub fn compare_oc3(self) -> &'a mut crate::W<REG> {
306        self.variant(MMS::CompareOc3)
307    }
308    ///OC4REF signal is used as trigger output
309    #[inline(always)]
310    pub fn compare_oc4(self) -> &'a mut crate::W<REG> {
311        self.variant(MMS::CompareOc4)
312    }
313}
314/**TI1 selection
315
316Value on reset: 0*/
317#[cfg_attr(feature = "defmt", derive(defmt::Format))]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum TI1S {
320    ///0: The TIMx_CH1 pin is connected to TI1 input
321    Normal = 0,
322    ///1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
323    Xor = 1,
324}
325impl From<TI1S> for bool {
326    #[inline(always)]
327    fn from(variant: TI1S) -> Self {
328        variant as u8 != 0
329    }
330}
331///Field `TI1S` reader - TI1 selection
332pub type TI1S_R = crate::BitReader<TI1S>;
333impl TI1S_R {
334    ///Get enumerated values variant
335    #[inline(always)]
336    pub const fn variant(&self) -> TI1S {
337        match self.bits {
338            false => TI1S::Normal,
339            true => TI1S::Xor,
340        }
341    }
342    ///The TIMx_CH1 pin is connected to TI1 input
343    #[inline(always)]
344    pub fn is_normal(&self) -> bool {
345        *self == TI1S::Normal
346    }
347    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
348    #[inline(always)]
349    pub fn is_xor(&self) -> bool {
350        *self == TI1S::Xor
351    }
352}
353///Field `TI1S` writer - TI1 selection
354pub type TI1S_W<'a, REG> = crate::BitWriter<'a, REG, TI1S>;
355impl<'a, REG> TI1S_W<'a, REG>
356where
357    REG: crate::Writable + crate::RegisterSpec,
358{
359    ///The TIMx_CH1 pin is connected to TI1 input
360    #[inline(always)]
361    pub fn normal(self) -> &'a mut crate::W<REG> {
362        self.variant(TI1S::Normal)
363    }
364    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
365    #[inline(always)]
366    pub fn xor(self) -> &'a mut crate::W<REG> {
367        self.variant(TI1S::Xor)
368    }
369}
370/**Output Idle state (OC%s output)
371
372Value on reset: 0*/
373#[cfg_attr(feature = "defmt", derive(defmt::Format))]
374#[derive(Clone, Copy, Debug, PartialEq, Eq)]
375pub enum OIS1 {
376    ///0: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
377    Reset = 0,
378    ///1: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
379    Set = 1,
380}
381impl From<OIS1> for bool {
382    #[inline(always)]
383    fn from(variant: OIS1) -> Self {
384        variant as u8 != 0
385    }
386}
387///Field `OIS(1-4)` reader - Output Idle state (OC%s output)
388pub type OIS_R = crate::BitReader<OIS1>;
389impl OIS_R {
390    ///Get enumerated values variant
391    #[inline(always)]
392    pub const fn variant(&self) -> OIS1 {
393        match self.bits {
394            false => OIS1::Reset,
395            true => OIS1::Set,
396        }
397    }
398    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
399    #[inline(always)]
400    pub fn is_reset(&self) -> bool {
401        *self == OIS1::Reset
402    }
403    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
404    #[inline(always)]
405    pub fn is_set(&self) -> bool {
406        *self == OIS1::Set
407    }
408}
409///Field `OIS(1-4)` writer - Output Idle state (OC%s output)
410pub type OIS_W<'a, REG> = crate::BitWriter<'a, REG, OIS1>;
411impl<'a, REG> OIS_W<'a, REG>
412where
413    REG: crate::Writable + crate::RegisterSpec,
414{
415    ///OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
416    #[inline(always)]
417    pub fn reset(self) -> &'a mut crate::W<REG> {
418        self.variant(OIS1::Reset)
419    }
420    ///OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
421    #[inline(always)]
422    pub fn set_(self) -> &'a mut crate::W<REG> {
423        self.variant(OIS1::Set)
424    }
425}
426/**Output Idle state (OC%sN output)
427
428Value on reset: 0*/
429#[cfg_attr(feature = "defmt", derive(defmt::Format))]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum OIS1N {
432    ///0: OCxN=0 after a dead-time when MOE=0
433    Reset = 0,
434    ///1: OCxN=1 after a dead-time when MOE=0
435    Set = 1,
436}
437impl From<OIS1N> for bool {
438    #[inline(always)]
439    fn from(variant: OIS1N) -> Self {
440        variant as u8 != 0
441    }
442}
443///Field `OISN(1-3)` reader - Output Idle state (OC%sN output)
444pub type OISN_R = crate::BitReader<OIS1N>;
445impl OISN_R {
446    ///Get enumerated values variant
447    #[inline(always)]
448    pub const fn variant(&self) -> OIS1N {
449        match self.bits {
450            false => OIS1N::Reset,
451            true => OIS1N::Set,
452        }
453    }
454    ///OCxN=0 after a dead-time when MOE=0
455    #[inline(always)]
456    pub fn is_reset(&self) -> bool {
457        *self == OIS1N::Reset
458    }
459    ///OCxN=1 after a dead-time when MOE=0
460    #[inline(always)]
461    pub fn is_set(&self) -> bool {
462        *self == OIS1N::Set
463    }
464}
465///Field `OISN(1-3)` writer - Output Idle state (OC%sN output)
466pub type OISN_W<'a, REG> = crate::BitWriter<'a, REG, OIS1N>;
467impl<'a, REG> OISN_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    ///OCxN=0 after a dead-time when MOE=0
472    #[inline(always)]
473    pub fn reset(self) -> &'a mut crate::W<REG> {
474        self.variant(OIS1N::Reset)
475    }
476    ///OCxN=1 after a dead-time when MOE=0
477    #[inline(always)]
478    pub fn set_(self) -> &'a mut crate::W<REG> {
479        self.variant(OIS1N::Set)
480    }
481}
482impl R {
483    ///Bit 0 - Capture/compare preloaded control
484    #[inline(always)]
485    pub fn ccpc(&self) -> CCPC_R {
486        CCPC_R::new((self.bits & 1) != 0)
487    }
488    ///Bit 2 - Capture/compare control update selection
489    #[inline(always)]
490    pub fn ccus(&self) -> CCUS_R {
491        CCUS_R::new(((self.bits >> 2) & 1) != 0)
492    }
493    ///Bit 3 - Capture/compare DMA selection
494    #[inline(always)]
495    pub fn ccds(&self) -> CCDS_R {
496        CCDS_R::new(((self.bits >> 3) & 1) != 0)
497    }
498    ///Bits 4:6 - Master mode selection
499    #[inline(always)]
500    pub fn mms(&self) -> MMS_R {
501        MMS_R::new(((self.bits >> 4) & 7) as u8)
502    }
503    ///Bit 7 - TI1 selection
504    #[inline(always)]
505    pub fn ti1s(&self) -> TI1S_R {
506        TI1S_R::new(((self.bits >> 7) & 1) != 0)
507    }
508    ///Output Idle state (OC(1-4) output)
509    ///
510    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
511    #[inline(always)]
512    pub fn ois(&self, n: u8) -> OIS_R {
513        #[allow(clippy::no_effect)]
514        [(); 4][n as usize];
515        OIS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0)
516    }
517    ///Iterator for array of:
518    ///Output Idle state (OC(1-4) output)
519    #[inline(always)]
520    pub fn ois_iter(&self) -> impl Iterator<Item = OIS_R> + '_ {
521        (0..4).map(move |n| OIS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0))
522    }
523    ///Bit 8 - Output Idle state (OC1 output)
524    #[inline(always)]
525    pub fn ois1(&self) -> OIS_R {
526        OIS_R::new(((self.bits >> 8) & 1) != 0)
527    }
528    ///Bit 10 - Output Idle state (OC2 output)
529    #[inline(always)]
530    pub fn ois2(&self) -> OIS_R {
531        OIS_R::new(((self.bits >> 10) & 1) != 0)
532    }
533    ///Bit 12 - Output Idle state (OC3 output)
534    #[inline(always)]
535    pub fn ois3(&self) -> OIS_R {
536        OIS_R::new(((self.bits >> 12) & 1) != 0)
537    }
538    ///Bit 14 - Output Idle state (OC4 output)
539    #[inline(always)]
540    pub fn ois4(&self) -> OIS_R {
541        OIS_R::new(((self.bits >> 14) & 1) != 0)
542    }
543    ///Output Idle state (OC(1-3)N output)
544    ///
545    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
546    #[inline(always)]
547    pub fn oisn(&self, n: u8) -> OISN_R {
548        #[allow(clippy::no_effect)]
549        [(); 3][n as usize];
550        OISN_R::new(((self.bits >> (n * 2 + 9)) & 1) != 0)
551    }
552    ///Iterator for array of:
553    ///Output Idle state (OC(1-3)N output)
554    #[inline(always)]
555    pub fn oisn_iter(&self) -> impl Iterator<Item = OISN_R> + '_ {
556        (0..3).map(move |n| OISN_R::new(((self.bits >> (n * 2 + 9)) & 1) != 0))
557    }
558    ///Bit 9 - Output Idle state (OC1N output)
559    #[inline(always)]
560    pub fn ois1n(&self) -> OISN_R {
561        OISN_R::new(((self.bits >> 9) & 1) != 0)
562    }
563    ///Bit 11 - Output Idle state (OC2N output)
564    #[inline(always)]
565    pub fn ois2n(&self) -> OISN_R {
566        OISN_R::new(((self.bits >> 11) & 1) != 0)
567    }
568    ///Bit 13 - Output Idle state (OC3N output)
569    #[inline(always)]
570    pub fn ois3n(&self) -> OISN_R {
571        OISN_R::new(((self.bits >> 13) & 1) != 0)
572    }
573}
574impl core::fmt::Debug for R {
575    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
576        f.debug_struct("CR2")
577            .field("ois1", &self.ois1())
578            .field("ois2", &self.ois2())
579            .field("ois3", &self.ois3())
580            .field("ois4", &self.ois4())
581            .field("ois1n", &self.ois1n())
582            .field("ois2n", &self.ois2n())
583            .field("ois3n", &self.ois3n())
584            .field("ti1s", &self.ti1s())
585            .field("mms", &self.mms())
586            .field("ccds", &self.ccds())
587            .field("ccus", &self.ccus())
588            .field("ccpc", &self.ccpc())
589            .finish()
590    }
591}
592impl W {
593    ///Bit 0 - Capture/compare preloaded control
594    #[inline(always)]
595    pub fn ccpc(&mut self) -> CCPC_W<CR2rs> {
596        CCPC_W::new(self, 0)
597    }
598    ///Bit 2 - Capture/compare control update selection
599    #[inline(always)]
600    pub fn ccus(&mut self) -> CCUS_W<CR2rs> {
601        CCUS_W::new(self, 2)
602    }
603    ///Bit 3 - Capture/compare DMA selection
604    #[inline(always)]
605    pub fn ccds(&mut self) -> CCDS_W<CR2rs> {
606        CCDS_W::new(self, 3)
607    }
608    ///Bits 4:6 - Master mode selection
609    #[inline(always)]
610    pub fn mms(&mut self) -> MMS_W<CR2rs> {
611        MMS_W::new(self, 4)
612    }
613    ///Bit 7 - TI1 selection
614    #[inline(always)]
615    pub fn ti1s(&mut self) -> TI1S_W<CR2rs> {
616        TI1S_W::new(self, 7)
617    }
618    ///Output Idle state (OC(1-4) output)
619    ///
620    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1` field.</div>
621    #[inline(always)]
622    pub fn ois(&mut self, n: u8) -> OIS_W<CR2rs> {
623        #[allow(clippy::no_effect)]
624        [(); 4][n as usize];
625        OIS_W::new(self, n * 2 + 8)
626    }
627    ///Bit 8 - Output Idle state (OC1 output)
628    #[inline(always)]
629    pub fn ois1(&mut self) -> OIS_W<CR2rs> {
630        OIS_W::new(self, 8)
631    }
632    ///Bit 10 - Output Idle state (OC2 output)
633    #[inline(always)]
634    pub fn ois2(&mut self) -> OIS_W<CR2rs> {
635        OIS_W::new(self, 10)
636    }
637    ///Bit 12 - Output Idle state (OC3 output)
638    #[inline(always)]
639    pub fn ois3(&mut self) -> OIS_W<CR2rs> {
640        OIS_W::new(self, 12)
641    }
642    ///Bit 14 - Output Idle state (OC4 output)
643    #[inline(always)]
644    pub fn ois4(&mut self) -> OIS_W<CR2rs> {
645        OIS_W::new(self, 14)
646    }
647    ///Output Idle state (OC(1-3)N output)
648    ///
649    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OIS1N` field.</div>
650    #[inline(always)]
651    pub fn oisn(&mut self, n: u8) -> OISN_W<CR2rs> {
652        #[allow(clippy::no_effect)]
653        [(); 3][n as usize];
654        OISN_W::new(self, n * 2 + 9)
655    }
656    ///Bit 9 - Output Idle state (OC1N output)
657    #[inline(always)]
658    pub fn ois1n(&mut self) -> OISN_W<CR2rs> {
659        OISN_W::new(self, 9)
660    }
661    ///Bit 11 - Output Idle state (OC2N output)
662    #[inline(always)]
663    pub fn ois2n(&mut self) -> OISN_W<CR2rs> {
664        OISN_W::new(self, 11)
665    }
666    ///Bit 13 - Output Idle state (OC3N output)
667    #[inline(always)]
668    pub fn ois3n(&mut self) -> OISN_W<CR2rs> {
669        OISN_W::new(self, 13)
670    }
671}
672/**control register 2
673
674You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
675
676See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM1:CR2)*/
677pub struct CR2rs;
678impl crate::RegisterSpec for CR2rs {
679    type Ux = u32;
680}
681///`read()` method returns [`cr2::R`](R) reader structure
682impl crate::Readable for CR2rs {}
683///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
684impl crate::Writable for CR2rs {
685    type Safety = crate::Unsafe;
686}
687///`reset()` method sets CR2 to value 0
688impl crate::Resettable for CR2rs {}
stm32f0/stm32f0x2/tim1/cr2.rs

stm32f0/stm32f0x2/tim1/
cr2.rs
